SBOSA18C may   2020  – june 2023 TSV911A-Q1 , TSV912A-Q1 , TSV914A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TSV911A-Q1
    5. 7.5 Thermal Information: TSV912A-Q1
    6. 7.6 Thermal Information: TSV914A-Q1
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input
      2. 8.3.2 Rail-to-Rail Output
      3. 8.3.3 Overload Recovery
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Input and ESD Protection
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-58A2EDD2-DB57-472A-A3B5-84AE7B42315A-low.svgFigure 6-1 TSV911A-Q1 DBV Package,
5-Pin SOT-23
(Top View)
GUID-C1B96E2B-930C-41B9-9086-3EA7BD6951F2-low.svgFigure 6-2 TSV911A-Q1 DCK Package,
5-Pin SC70
(Top View)
Table 6-1 Pin Functions: TSV911A-Q1
PIN TYPE(1) DESCRIPTION
NAME SOT-23 SC70
IN– 4 3 I Inverting input
IN+ 3 1 I Noninverting input
OUT 1 4 O Output
V– 2 2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 I Positive (high) supply
(1) I = input, O = output
GUID-8E9A7C42-C6DA-4C20-BA20-2C6217D23BF8-low.svg Figure 6-3 TSV912A-Q1 D, PW and DGK Packages,
8-Pin SOIC, TSSOP and VSSOP
(Top View)
Table 6-2 Pin Functions: TSV912A-Q1
PIN TYPE(1) DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
+IN A 3 I Noninverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Noninverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V– 4 — Negative (lowest) supply or ground (for single-supply operation)
V+ 8 — Positive (highest) supply
(1) I = input, O = output
GUID-D093D7D3-F7EA-4AE5-B57C-205EFD8C8407-low.svg Figure 6-4 TSV914A-Q1 D and PW Packages,
14-Pin SOIC and TSSOP
(Top View)
Table 6-3 Pin Functions: TSV914A-Q1
PIN TYPE(1) DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
+IN A 3 I Noninverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Noninverting input, channel B
–IN C 9 I Inverting input, channel C
+IN C 10 I Noninverting input, channel C
–IN D 13 I Inverting input, channel D
+IN D 12 I Noninverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V– 11 — Negative (lowest) supply or ground (for single-supply operation)
V+ 4 — Positive (highest) supply
(1) I = input, O = output