SLLSEU4E May   2016  – May 2019 TUSB1002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Power Supply
    6. 6.6  Electrical Characteristics
    7. 6.7  Power-Up Requirements
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Control Inputs
      2. 7.3.2 Linear Equalization
      3. 7.3.3 Adjustable VOD Linear Range and DC Gain
      4. 7.3.4 Receiver Detect Control
      5. 7.3.5 USB3.1 Dual Channel Operation (MODE = “F”)
      6. 7.3.6 USB3.1 Single Channel Operation (MODE = “1”)
      7. 7.3.7 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Disconnect Mode
    5. 7.5 U0 Mode
    6. 7.6 U1 Mode
    7. 7.7 U2/U3 Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical USB3.1 Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical SATA, PCIe and SATA Express Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4-Level Inputs (MODE, CFG1, CFG2,CH1_EQ1, CH1_EQ2, CH2_EQ1, CH2_EQ2 )
IIH High level input current VCC = 3.6 V; VIN = 3.6 V 20 80 μA
IIL Low level input current VCC = 3.6 V; VIN = 0 V –160 –40 μA
VTH Threshold 0 / R VCC = 3.3 V 0.55 V
Threshold R/ Float 1.65 V
Threshold Float / 1 2.8 V
RPU Internal pull-up resistance 45 kΩ
RPD Internal pull-down resistance 95 kΩ
EN, SLP_S0# Input
VIH High level input voltage VCC = 3. V 1.7 VCC V
VIL Low level input voltage VCC = 3.3 V 0 0.7 V
IIH High level input current VCC = 3.6 V, EN = 3.6 V –10 10 µA
IIL Low level input current VCC = 3.6 V, EN = 0 V –15 15 µA
R(EN-PU) Internal pull-up resistance for EN and SLP_S0#. 400 kΩ
USB3.1 RECEIVER INTERFACE (RX1P/N AND RX2P/N)
RL(RX-DIFF) RX Differential return loss SDD11 10 MHz at 90 Ω –19 dB
SDD11 2 GHz at 90 Ω –14 dB
SDD11 5 – 10 GHz at 90 Ω –7 dB
RL(RX-CM) RX Common mode return loss 0.5 – 5 GHz at 90 Ω –10 dB
X-TALK Differential crosstalk between TX and RX signal pairs. -50 dB
EQ(GAIN-10Gbps) Equalization Gain 50 mVpp At 5 GHz 16 dB
EQ(DC0) DC Equalization Gain at 0dB setting. 500 mVpp VID at 100 MHz; 1200mV Linear Range Setting; Refer to Table 3 -0.15 dB
EQ(DC1) DC Equalization Gain at +1dB setting. 500 mVpp VID at 100 MHz; 1200mV Linear Range Setting; 0.80 dB
EQ(DC2) DC Equalization Gain at +2dB setting. 500 mVpp VID at 100 MHz; 1000mV Linear Range Setting; 1.5 dB
EQ(DC-1) DC Equalization Gain at -1dB setting. 500 mVpp VID at 100 MHz; 1200mV Linear Range Setting; –1.1 dB
EQ(DC-2) DC Equalization Gain at -2dB setting. 500 mVpp VID at 100 MHz; 1200mV Linear Range Setting; –2.05 dB
V(DIFF_IN) Input differential peak-peak voltage swing range. 2000 mV
V(RX-DC-CM) RX DC common mode voltage 1.65 1.85 2.0 V
R(RX-CM-DC) Receiver DC common mode impedance Measured at connector. Present when SuperSpeed USB device detected on TXP/N 18 30 Ω
R(RX-DIFF-DC) Receiver DC differential impedance Measured at connector. Present when SuperSpeed USB device detected on TXP/N; SLP_S0# = 1; 72 120 Ω
Z(RX-HIGH-IMP-DC-POS) DC input CM input impedance when termination is disabled. Measured at connector. Present when no SuperSpeed USB device detected on TXP/N or while VCC is ramping 30 KΩ
V(RX-SIGNAL_DET_DIFF-PP) Input differential peak-to-peak Signal Detect Assert level at 10 Gbps. No loss input channel and PRBS7 pattern 92 mV
V(RX-IDLE_DET_DIFF-PP) Input differential peak-to-peak Signal Detect De-assert Level at 10 Gbps. No loss input channel and PRBS7 pattern 62 mV
V(RX-LFPS-DET-DIFF-P-P) LFPS Detect threshold. Below min is noise. Measured at connector. Below min is squelched 100 300 mV
V(RX-CM-AC-P) Peak RX AC common mode voltage Measured at package pin 150 mV
C(RX-PARASITIC) Rx Input capacitance for return loss At package pin 0.5 pF
USB3.1 Transmitter Interface (TX1P/N and TX2P/N)
RL(TX-DIFF) TX Differential return loss SDD22 10MHz – 2 GHz at 90 Ω –15 dB
SDD22 5 GHz at 90 Ω –11 dB
SDD22 5 - 10 GHz at 90 Ω –7 dB
RL(TX-CM) TX Common Mode return loss 0.05 – 5 GHz at 90 Ω –9 dB
V(TX-DIFF-PP_1200) Differential peak-to-peak TX voltage swing linear dynamic range CFG1 pin = F or 1; Refer to Table 3 Measured at -1dB compression point = 20log (VOD/VOD_linear) 1200 1450 mV
V(TX-DIFF-PP_1000) Differential peak-to-peak TX voltage swing linear dynamic range CFG1 pin = R; Refer to Table 3 Measured at -1dB compression point = 20log (VOD/VOD_linear) 1000 mV
V(TX-DIFF-PP_900) Differential peak-to-peak TX voltage swing linear dynamic range CFG1 pin = 0; Refer to Table 3Measured at -1dB compression point = 20log (VOD/VOD_linear) 900 mV
V(TX-RCV-DETECT) The amount of voltage change allowed during Receiver Detection. 600 mV
V(TX-CM-IDLE-DELTA) Transmitter idle common-mode voltage change while in U2/3 and not actively transmitting LFPS. –600 600 mV
V(TX-DC-CM) TX DC common mode voltage 1200mVpp Linear Range setting. 0 1.85 2 V
V(TX-IDLE-DIFF-AC-PP) AC Electrical Idle differential peak-to-peak output voltage At package pin. 0 10 mV
V(TX-IDLE-DIFF_DC) DC Electrical Idle differential output voltage At package pin. After low pass filter to remove AC component. 0 14 mV
V(TX-CM-AC-PP) Transmitter AC common mode peak-peak voltage in U0 1200mVpp linear range; CHx_EQ setting matches input channel insertion loss; 80 mV
V(TX-CM-DC-ACTIVE-IDLE-DELTA) Absolute DC common mode voltage between U1 and U0. At package pin. 200 mV
I(TX-SHORT) TX short-circuit current limit 106 mA
R(TX-DC) TX DC common mode impedance At package pin 18 30 Ω
R(TX-DIFF-DC) TX DC differential impedance 72 90 120 Ω
C(TX-PARASTIC) TX input capacitance for return loss At package pin 0.7 pF
C(AC-COUPLING) External AC Coupling capacitor on differential pairs. 75 265 nF