SLLSFP2 September 2024 TUSB1021-Q1
PRODUCTION DATA
Each of the TUSB1021-Q1 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. The following table details the gain value for each available combination when TUSB1021-Q1 is in GPIO mode. These same options are also available in I2C mode by updating registers EQ1_SEL, EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R = 01, F = 10, 1 = 11.
| EQUALIZATION SETTING # | RX1 and RX2 PORTS | SSTX PORT | ||||
|---|---|---|---|---|---|---|
| EQ1 PIN LEVEL | EQ0 PIN LEVEL | EQ GAIN AT 5GHz (dB) | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ GAIN AT 5GHz (dB) | |
| 0 | 0 | 0 | 0.4 | 0 | 0 | –2.4 |
| 1 | 0 | R | 2.6 | 0 | R | –0.2 |
| 2 | 0 | F | 4.2 | 0 | F | 1.3 |
| 3 | 0 | 1 | 5.7 | 0 | 1 | 2.8 |
| 4 | R | 0 | 6.7 | R | 0 | 3.8 |
| 5 | R | R | 7.9 | R | R | 4.9 |
| 6 | R | F | 8.7 | R | F | 5.8 |
| 7 | R | 1 | 9.5 | R | 1 | 6.6 |
| 8 | F | 0 | 10.2 | F | 0 | 7.3 |
| 9 | F | R | 10.9 | F | R | 7.9 |
| 10 | F | F | 11.4 | F | F | 8.4 |
| 11 | F | 1 | 11.9 | F | 1 | 8.9 |
| 12 | 1 | 0 | 12.2 | 1 | 0 | 9.3 |
| 13 | 1 | R | 12.6 | 1 | R | 9.7 |
| 14 | 1 | F | 12.9 | 1 | F | 10.0 |
| 15 | 1 | 1 | 13.3 | 1 | 1 | 10.5 |