The TUSB1042I is a redriving switch supporting USB 3.1 data rates up to 10 Gbps. The TUSB1042I provides several levels of receive linear equalization to compensate for inter-symbol interference (ISI) due to cable and board trace loss. The device operates on a single 3.3 V supply and comes in the industrial temperature range.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TUSB1042I | WQFN (40) | 4.00 mm x 6.00 mm |
Changes from C Revision (August 2018) to D Revision
Changes from B Revision (April 2018) to C Revision
Changes from A Revision (October 2017) to B Revision
Changes from * Revision (August 2017) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RX1n | 31 | Diff I/O | Differential negative input for USB3.1 Downstream Facing port. |
RX1p | 30 | Diff I/O | Differential positive input for USB3.1 Downstream Facing port. |
TX1n | 34 | Diff O | Differential negative output for USB3.1 downstream facing port. |
TX1p | 33 | Diff O | Differential positive output for USB 3.1 downstream facing port. |
TX2p | 37 | Diff O | Differential positive output for USB 3.1 downstream facing port. |
TX2n | 36 | Diff O | Differential negative output for USB 3.1 downstream facing port. |
RX2p | 40 | Diff I/O | Differential positive input for USB3.1 Downstream Facing port. |
RX2n | 39 | Diff I/O | Differential negative input for USB3.1 Downstream Facing port. |
SSTXp | 8 | Diff I | Differential positive input for USB3.1 upstream facing port. |
SSTXn | 7 | Diff I | Differential negative input for USB3.1 upstream facing port. |
SSRXp | 5 | Diff O | Differential positive output for USB3.1 upstream facing port. |
SSRXn | 4 | Diff O | Differential negative output for USB3.1 upstream facing port. |
EQ1 | 35 | 4 Level I | This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. |
EQ0 | 38 | 4 Level I | This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. |
DCI_DAT | 29(1) | I/O
(PD) |
When I2C_EN ! = 0, this pin functions as DCI data output Leave open if not used. |
DCI_CLK | 32(1) | I/O
(PD) |
When I2C_EN ! = 0, this pin functions as DCI clock output Leave open if not used. |
I2C_EN | 17 | 4 Level I | I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled) R = TI Test Mode (I2C enabled at 3.3 V) F = I2C enabled at 1.8 V 1 = I2C enabled at 3.3 V. |
A1 | 14 | 4 Level I | When I2C_EN is not ‘0’, this pin will set the TUSB1042I I2C address. |
SSEQ1 | 3 | 4 Level I | Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N. |
SSEQ0/A0 | 11 | 4 Level I | Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When I2C_EN is not ‘0’, this pin will also set the TUSB1042I I2C address. If I2C_EN = “F”, then this pin must be set to “F” or “0”. |
FLIP/SCL | 21 | 2 Level I | When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C master's VCC I2C supply. |
CTL0/SDA | 22 | 2 Level I | When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for I2C data pullup to I2C master's VCC I2C supply. |
RSVD1 - 12 | 9, 10, 12, 13, 15, 16, 18, 19, 24, 25, 26, 27 | RSVD | Reserved. Leave open. |
TEST1 | 23 | 2 Level I
(Failsafe) (PD) |
Test pin. Pull down to GND. |
TEST2 | 2 | 4 Level I | Test pin. Leave open. |
VCC | 1, 6, 20, 28 | P | 3.3-V Power Supply |
Thermal Pad | G | Ground |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage Range(2), VCC | –0.3 | 4 | V | |
Voltage Range at any input or output pin | Differential voltage between positive and negative inputs | ±2.5 | V | |
Voltage at differential inputs | –0.5 | VCC + 0.5 | V | |
CMOS Inputs | –0.5 | VCC + 0.5 | V | |
Maximum junction temperature, TJ | 125 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±5000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Main power supply | 3 | 3.3 | 3.6 | V | |
Supply Ramp Requirement | 100 | ms | ||||
V(12C) | Supply that external resistors are pulled up to on SDA and SCL | 1.7 | 3.6 | V | ||
V(PSN) | Supply Noise on VCC pins | 100 | mV | |||
TA | Operating free-air temperature | TUSB1042I | -40 | 85 | °C |
THERMAL METRIC(1) | TUSB1042I | UNIT | |
---|---|---|---|
RNQ (WQFN) | |||
40 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 37.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 20.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 9.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 9.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PCC(ACTIVE-USB) | Average active power
USB Only |
Link in U0 with GEN2 data transmission. EN, EQ cntrl pins = NC, k28.5 pattern at
10 Gbps, VID = 1000 mVPP ; CTL1 = L; CTL0 = H |
335 | mW | ||
PCC(ACTIVE-USB-DP1) | Average active power
USB + 2 Lane DP |
Link in U0 with GEN2 data transmission. EN, EQ cntrl pins = NC, k28.5 pattern at
10 Gbps, VID = 1000 mVPP; CTL1 = H; CTL0 = H |
634 | mW | ||
PCC(ACTIVE--DP) | Average active power
4 Lane DP Only |
Four active DP lanes operating at 8.1Gbps;
CTL1 = H; CTL0 = L; |
660 | mW | ||
PCC(NC-USB) | Average power with no connection | No GEN1 device is connected to TXP/TXN;
CTL1 = L; CTL0 = H; |
2.4 | mW | ||
PCC(U2U3) | Average power in U2/U3 | Link in U2 or U3 USB Mode Only;
CTL1 = L; CTL0 = H; |
3 | mW | ||
PCC(SHUTDOWN) | Device Shutdown | CTL1 = L; CTL0 = L; I2C_EN = 0; | 0.85 | mW |