SLLSF15D August   2017  – May 2019 TUSB1042I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematics
      2.      TUSB1042I Eye Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 USB3.1 Modes
      5. 8.4.5 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 9. General Registers
      2. 8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 10. USB3.1 Control/Status Registers (0x20)
      3. 8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 11. USB3.1 Control/Status Registers (0x21)
      4. 8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 12. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.3 Linear EQ Configuration

Each of the TUSB1042I receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 5 details the gain value for each available combination when TUSB1042I is in GPIO mode. These same options are also available in I2C mode by updating registers EQ1_SEL, EQ2_SEL, and SSEQ_SEL.

Table 5. TUSB1042I Receiver Equalization GPIO Control

Equalization Setting # USB3.1 DOWNSTREAM FACING PORTS USB 3.1 UPSTREAM FACING PORT
EQ1 PIN LEVEL EQ0 PIN LEVEL EQ GAIN at 5 GHz (dB) SSEQ1 PIN LEVEL SSEQ0 PIN LEVEL EQ GAIN at 5 GHz (dB)
0 0 0 -3.9 0 0 -1.8
1 0 R -1.7 0 R 0.2
2 0 F -0.1 0 F 1.7
3 0 1 1.4 0 1 3.2
4 R 0 2.4 R 0 4.2
5 R R 3.5 R R 5.3
6 R F 4.4 R F 6.1
7 R 1 5.2 R 1 7.0
8 F 0 5.9 F 0 7.7
9 F R 6.6 F R 8.3
10 F F 7.1 F F 8.8
11 F 1 7.6 F 1 9.3
12 1 0 8.0 1 0 9.7
13 1 R 8.5 1 R 10.1
14 1 F 8.8 1 F 10.4
15 1 1 9.2 1 1 10.8