SLLSF13B June   2017  – May 2019 TUSB1046A-DCI

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematics
      2.      TUSB1046A-DCI Eye Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 11. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 12. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 13. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 14. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 15. DisplayPort Control/Status Registers (0x13)
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 16. USB3.1 Control/Status Registers (0x20)
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 17. USB3.1 Control/Status Registers (0x21)
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 18. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Device Configuration in GPIO Mode

The TUSB1046A-DCI is in GPIO configuration when I2C_EN = “0”. The TUSB1046A-DCI supports the following configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXp or AUXn to SBU1 or SBU2 mapping is controlled based on Table 3.

After power-up (VCC from 0 V to 3.3 V), the TUSB1046A-DCI defaults to USB3.1 mode. The USB PD controller upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take TUSB1046A-DCI out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.

Table 2. GPIO Configuration Control

CTL1 PIN CTL0 PIN FLIP PIN TUSB1046A-DCI CONFIGURATION VESA DisplayPort ALT MODE
DFP_D CONFIGURATION
L L L Power Down —
L L H Power Down —
L H L One Port USB 3.1 - No Flip —
L H H One Port USB 3.1 – With Flip —
H L L 4 Lane DP - No Flip C and E
H L H 4 Lane DP – With Flip C and E
H H L One Port USB 3.1 + 2 Lane DP- No Flip D and F
H H H One Port USB 3.1 + 2 Lane DP– With Flip D and F

Table 3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping

CTL1 PIN FLIP PIN MAPPING
H L AUXp → SBU1
AUXn → SBU2
H H AUXp → SBU2
AUXn → SBU1
L > 2 ms X Open

Table 4 Details the TUSB1046A-DCI’s mux routing. This table is valid for both I2C and GPIO configuration modes.

Table 4. INPUT to OUTPUT Mapping

CTL1 PIN CTL0 PIN FLIP PIN FROM TO
INPUT PIN OUTPUT PIN
L L L NA NA
L L H NA NA
L H L RX1P SSRXP
RX1N SSRXN
SSTXP TX1P
SSTXN TX1N
L H H RX2P SSRXP
RX2N SSRXN
SSTXP TX2P
SSTXN TX2P
H L L DP0P RX2P
DP0N RX2N
DP1P TX2P
DP1N TX2N
DP2P TX1P
DP2N TX1N
DP3P RX1P
DP3N RX1N
H L H DP0P RX1P
DP0N RX1N
DP1P TX1P
DP1N TX1N
DP2P TX2P
DP2N TX2N
DP3P RX2P
DP3N RX2N
H H L RX1P SSRXP
RX1N SSRXN
SSTXP TX1P
SSTXN TX1N
DP0P RX2P
DP0N RX2N
DP1P TX2P
DP1N TX2N
H H H RX2P SSRXP
RX2N SSRXN
SSTXP TX2P
SSTXN TX2N
DP0P RX1P
DP0N RX1N
DP1P TX1P
DP1N TX1N