SLLSFL2A April 2022 – May 2024 TUSB1142
PRODUCTION DATA
Table 7-9 lists the memory-mapped registers for the TUSB1142 registers. All register offset addresses not listed in Table 7-9 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
8h | Rev_ID | Revision ID Register | Go |
Ah | General_1 | General Register | Go |
Bh | TX1EQ_CTRL | TX1 EQ Control | Go |
1Ch | AEQ_CONTROL1 | AEQ Controls | Go |
1Dh | AEQ_CONTROL2 | AEQ Controls | Go |
1Eh | AEQ_LONG | AEQ setting for Long channel | Go |
20h | USBC_EQ | EQ control for CRX1 and CRX2 receivers | Go |
21h | SS_EQ | EQ Control for SSTX receiver | Go |
22h | USB3_MISC | Misc USB3 Controls | Go |
24h | USB1_STATUS | USB1 state machine status | Go |
25h | USB2_STATUS | USB2 state machine status | Go |
32h | VOD_CTRL | VOD Linearity and AEQ Controls | Go |
3Bh | AEQ1_STATUS | Full and Fast AEQ status | Go |
3Ch | AEQ2_STATUS | Full and Fast AEQ status | Go |
50h | AEQ_CONTROL_AUX1 | Go | |
51h | AEQ_CONTROL_AUX2 | Go | |
52h | AEQ_CONTROL_AUX3 | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | R H | Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WtoPH | W toPH | Write Pulse high |
Reset or Default Value | ||
-n | Value after reset or the default value |
Rev_ID is shown in Table 7-11.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REVISION_ID | RH | 1h | Device Revision |
General_1 is shown in Table 7-12.
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This register is used to enable USB as well as selecting the orientation of the MUX. Software should set EQ_OVERRIDE bit in order for EQ registers to be used instead of pins.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SSRX_LIMIT_ENABLE | R/W | 0h | Limited redriver mode enable for SSRX transmitter.
0h = Linear Redriver 1h = Limited Redriver |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | EQ_OVERRIDE | R/W | 0h | Setting this field will allow software to use EQ settings from registers instead of value sampled from pins.
0h = EQ settings based on sampled state of EQ pins. 1h = EQ settings based on programmed value of each of the EQ registers. |
3 | RESERVED | R | 0h | Reserved |
2 | FLIP_SEL | R/W | 0h | This field controls the orientation.
0h = Normal Orientation 1h = Flip orientation. |
1-0 | CTLSEL | R/W | 0h | Controls whether USB is enabled or not.
0h = Disabled 1h = USB enabled. 2h = Disabled 3h = USB enabled |
TX1EQ_CTRL is shown in Table 7-13.
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This register controls the preshoot and de-emphasis levels for SSRX when limited redriver mode is enabled.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SSRX_PRESHOOT | R/W | 1h | SSRX TX preshoot level (pre-cursor).
0h = 1.5dB 1h = 2dB 2h = 2.3dB 3h = 2.8dB |
5 | SSRX_PRESHOOT_EN | R/W | 1h | SSRX TX preshoot (pre-cursor) enabled. Valid only when SSRX_LIMIT_ENABLE = 1.
0h = Disabled (0dB) 1h = Enabled |
4-3 | SSRX_DEEMPHASIS | R/W | 1h | SSRX TX de-emphasis level (post-cursor)
0h = -1.5dB 1h = -2.1dB 2h = -3.2dB 3h = -3.8dB |
2 | SSRX_DEEMPHASIS_EN | R/W | 1h | SSRX TX de-emphasis (post-cursor) enable. Valid only when SSRX_LIMIT_ENABLE = 1.
0h = Disabled (0dB) 1h = Enabled |
1-0 | RESERVED | R/W | 3h | Reserved |
AEQ_CONTROL1 is shown in Table 7-14.
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This register is used to enable adaptive EQ and select between Fast and Full adaptive EQ.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | FULLAEQ_UPPER_EQ | R/W | 8h | This field sets the maximum EQ value to check for full AEQ mode when in I2C mode. |
3 | USB3_U1_DISABLE | R/W | 0h | This field when set will cause entry to U3 instead of U1 when electrical idle is detected.
0h = U1 entry after electrical idle. 1h = U3 entry after electrical idle. |
2-1 | AEQ_MODE | R/W | 2h | Selects Adaption mode (Fast, or one of three Full modes).
0h = Fast AEQ. 1h = Full AEQ, with hits counted at mideye for every EQ iteration (using current EQ setting). 2h = Full AEQ, algorithm II. 3h = Full AEQ, with hits counted at mideye only for first EQ iteration (using EQ set to the MID_HC_EQ value). |
0 | AEQ_EN | R/W | 1h | Controls whether or not adaptive EQ for USB downstream facing port is enabled.
0h = AEQ disabled 1h = AEQ enabled |
AEQ_CONTROL2 is shown in Table 7-15.
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This register allows for controls for the Fast AEQ limits as well as adding or reducing final EQ value used by the Full AEQ function.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | OVER_EQ_SIGN | R/W | 0h | Selects the sign for OVER_EQ_CTRL field.
0h = positive 1h = negative |
6 | RESERVED | R | 0h | Reserved |
5-3 | FASTAEQ_LIMITS | R/W | 2h | Selects the upper/lower limits of DAC for determining short vs long channel.
0h = +/- 0mV 1h = +/- 40mV 2h = +/- 80mV 3h = +/- 120mV 4h = +/- 160mV 5h = +/- 200mV 6h = +/- 240mV 7h = +/- 280mV |
2-0 | OVER_EQ_CTRL | R/W | 0h | This field will increase or decrease the AEQ by value programmed into this field. For example, full AEQ value is 6 and this field is programmed to 2 and OVER_EQ_SIGN = 0, then EQ value used will be 8. This field is only used in Full AEQ mode.
0h = 0 or -8 1h = 1 or -7 2h = 2 or -6 3h = 3 or -5 4h = 4 or -4 5h = 5 or -3 6h = 6 or -2 7h = 7 or -1 |
AEQ_LONG is shown in Table 7-16.
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This register is used to program the EQ used for long channel setting when Fast AEQ is enabled.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | LONG_CEQ2 | R/W | 7h | When AEQ_EN = 1 and AEQ_MODE = x0 (that is, Fast), selects EQ setting for USB connector port2 (CRX2) when long channel is detected. The user should program this field with the value that provides the best Rx JTOL results for a long channel configuration. |
3-0 | LONG_CEQ1 | R/W | 7h | When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB connector port1 (CRX1) when long channel is detected. The user should program this field with the value that provides the best Rx JTOL results for a long channel configuration. |
USBC_EQ is shown in Table 7-17.
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This register controls the receiver equalization setting for the connector receiver (CRX1 and CRX2).
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CEQ2_SEL | RH/W | 0h | If AEQ_EN = 0, this field selects EQ for USB CRX2 receiver which faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field reflects the sampled state of CEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for CRX2p/n pins based on value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB connector port2 (CRX2) when short channel is detected. The user should program this field with the value that provides the best Rx JTOL results for a short channel configuration. |
3-0 | CEQ1_SEL | RH/W | 0h | If AEQ_EN = 0, this field selects EQ for USB CRX1 receiver which faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field reflects the sampled state of CEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for CRX1p/n pins based on value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB connector port1 (CRX1) when short channel is detected. The user should program this field with the value that provides the best Rx JTOL results for a short channel configuration. |
SS_EQ is shown in Table 7-18.
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This register controls the receiver equalization setting for the SSTX.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | RH/W | 0h | Reserved |
3-0 | SSEQ1_SEL | RH/W | 0h | This field selects EQ for USB SSTX receiver which faces the USB host. When EQ_OVERRIDE = 0b, this field reflects the sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for SSTXp/n pins based on value written to this field. |
USB3_MISC is shown in Table 7-19.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RXD_START_TERM | R/W | 0h | Termination setting at start of RX detection following warm reset and at entry to SS.Inactive.
0h = Maintain termination. 1h = Turn off termination. Avoid compliance failures due to race between local and remote rxd in case of disconnect. If connection remains next state was polling regardless. |
6-5 | U23_RXDET_INTERVAL | R/W | 0h | This field controls the Rx.Detect interval for the downstream facing port (CTX1P/N and CTX2P/N) when in U2/U3.
0h = 48ms 1h = 84ms 2h = 120ms 3h = 156ms |
4 | DISABLE_U2U3_RXDET | R/W | 0h | Controls whether or not Rx.Detect is performed in U2/U3 state.
0h = Rx.Detect in U2/U3 enabled. 1h = Rx.Detect in U2/U3 disabled. |
3-2 | DFP_RXDET_INTERVAL | R/W | 1h | This field controls the Rx.Detect interval for the downstream facing port (CTX1P/N and CTX2P/N).
0h = 4ms 1h = 6ms 2h = 36ms 3h = 84ms |
1 | DIS_WARM_RESET_RXD | R/W | 0h | Disables receiver detection following warm reset if device starts polling during warm reset.
0h = whether receiver detection is done following warm reset depends on other settings. 1h = if USB FSM detects that device started polling during warm reset, it will not do receiver detection. |
0 | USB_COMPLIANCE_CTRL | R/W | 0h | Controls whether compliance mode detection is determined by FSM or disabled
0h = Compliance mode determined by FSM. 1h = Compliance mode disabled. |
USB1_STATUS is shown in Table 7-20.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | USB1_FASTAEQ_STAT | RH | 0h | When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates whether short or long EQ setting is used. When AEQ_EN = 0, this field will always default to 0h.
0h = Short channel EQ used. 1h = Long channel EQ used. |
6 | RESERVED | RH/W1C | 0h | Reserved |
5 | RESERVED | RH | 0h | Reserved |
4 | RESERVED | RH | 0h | Reserved |
3 | CM_ACTIVE1 | RH | 0h | Compliance mode status.
0h = Not in USB3.1 compliance mode. 1h = In USB3.1 compliance mode. |
2 | U0_STAT1 | RH | 0h | U0 Status. Set if enters U0 state. |
1 | U2U3_STAT1 | RH | 0h | U2/U3 Status. Set if enters U2/U3 state. |
0 | DISC_STAT1 | RH | 1h | Disconnect Status. Set if enters Disconnect state. |
USB2_STATUS is shown in Table 7-21.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | USB2_FASTAEQ_STAT | RH | 0h | When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates whether short or long EQ setting is used. When AEQ_EN = 0, this field will always default to 0h.
0h = Short channel EQ used. 1h = Long channel EQ used. |
6 | RESERVED | RH/W1C | 0h | Reserved |
5 | RESERVED | RH | 0h | Reserved |
4 | RESERVED | RH | 0h | Reserved |
3 | CM_ACTIVE2 | RH | 0h | Compliance mode status.
0h = Not in USB3.1 compliance mode. 1h = In USB3.1 compliance mode. |
2 | U0_STAT2 | RH | 0h | U0 Status. Set if enters U0 state. |
1 | U2U3_STAT2 | RH | 0h | U2/U3 Status. Set if enters U2/U3 state. |
0 | DISC_STAT2 | RH | 1h | Disconnect Status. Set if enters Disconnect state. |
VOD_CTRL is shown in Table 7-22.
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This register controls the transmitters output linearity range for both UFP and DFP. When device is configured for limited redriver (SSRX_LIMIT_ENABLE field is set), USB_SSRX_VOD controls the VOD level for SSRX limited driver.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LFPS_VOD | R/W | 3h | VOD linearity control for SSRX, CTX1, and CTX2 when LFPS is being transmitted.
0h = LINR_L3 (highest) 1h = LINR_L2 2h = LINR_L1 3h = LINR_L0 (lowest) |
5-4 | RESERVED | R | 0h | Reserved |
3-2 | USB_CTX12_VOD | R/W | 0h | VOD linearity control for USB connector facing ports (CTX1 and CTX2).
0h = LINR_L3 (highest) 1h = LINR_L2 2h = LINR_L1 3h = LINR_L0 (lowest) |
1-0 | USB_SSRX12_VOD | R/W | 0h | VOD linearity control for USB upstream facing port (SSRX). When SSRX_LIMIT_ENABLE = 1, then this field controls the limited VOD for SSRX.
0h = LINR_L3 (highest) 1h = LINR_L2 2h = LINR_L1 3h = LINR_L0 (lowest) |
AEQ1_STATUS is shown in Table 7-23.
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This register provides the status of AEQ function.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | RH | 0h | Reserved |
3-0 | AEQ1_EQ_STAT | RH | 0h | Optimal EQ determined by FSM after the completion of Full AEQ. This field will also indicate EQ used for Fast AEQ. This field will include the value programmed into OVER_EQ_CTRL field. |
AEQ2_STATUS is shown in Table 7-24.
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This register provides the status of AEQ function.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | RH | 0h | Reserved |
3-0 | AEQ2_EQ_STAT | RH | 0h | Optimal EQ determined by FSM after the completion of Full AEQ. This field will also indicate EQ used for Fast AEQ. This field will include the value programmed into OVER_EQ_CTRL field. |
AEQ_CONTROL_AUX1 is shown in Table 7-25.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5-2 | RESERVED | R | 0h | Reserved |
1-0 | RESERVED | R | 0h | Reserved |
AEQ_CONTROL_AUX2 is shown in Table 7-26.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | EQ_MERGE | R/W | 0h | Initial EQ result merge control. This field controls how the EQ results from the positive and negative VOD offsets steps are merged to produce the initial EQ value.
This field is applicable only when the AEQ_MODE field is set to 2'b10.
0h = Use max of pos/neg VOD EQs 1h = Use min of pos/neg VOD EQs |
3-0 | MID_HC_EQ | R/W | 7h | Sets EQ value during the mid-eye hit-count capture step. This field is applicable only when the AEQ_MODE field is set to 2'b10 or 2'b11. |
AEQ_CONTROL_AUX3 is shown in Table 7-27.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | HC_EQ_THR | R/W | 4h | Sets the hit-count threshold during the EQ search steps. The algorithm will find the minimum EQ setting such that the hit-count is at or above value N_eq, where: N_eq = HC_me * (128-HC_EQ_THR)/128 and HC_me is the mid-eye hit-count. This field is applicable only when the AEQ_MODE field is set to 2'b10. |
4 | RESERVED | R | 0h | Reserved |
3-0 | HC_VOD_THR | R/W | 6h | Sets the hit-count threshold during the VOD search steps. The algorithm will find the maximum DAC VOD setting such that the hit-count is at or above the threshold value N_vod, where: N_vod = HC_me * HC_VOD_THR/128 and HC_me is the mid-eye hit-count. This field is applicable only when the AEQ_MODE field is set to 2'b10. |