SLLSFL2A April   2022  – May 2024 TUSB1142

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.2 2:1 MUX Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1142 I2C Address Options
      3. 7.5.3 TUSB1142 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 TUSB1142 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB SSTX Receiver Configuration
        2. 8.2.2.2 USB CRX1/2 Receiver Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Full Adaptive Equalization
          3. 8.2.2.2.3 Fast Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Control I/O DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4-level Inputs
4-Level VTH Threshold 0 / R VCC = 3.3 V 0.55 V
4-Level VTH Threshold R/ Float VCC = 3.3 V 1.65 V
4-Level VTH Threshold Float / 1 VCC33 = 3.3 V 2.7 V
IIH High level input current with internal resistors disabled. VCC = 3.6 V; VIN = 3.6 V -5 5 µA
IIL Low level input current with internal resistors disabled VCC = 3.6 V; VIN = 0 V -1 1 µA
IIH-REN High level input current with internal resistors enabled. VCC = 3.6 V; VIN = 3.6 V 20 60 µA
IIL-REN Low level input current with internal resistors enabled. VCC = 3.6 V; VIN = 0 V –100 -40 µA
RPU Internal pullup resistance 48 kΩ
RPD Internal pulldown resistance 98 kΩ
2-State CMOS Input (EN, SLP_S0#)
VIH High-level input voltage 1.2 3.6 V
VIL Low-level input voltage -0.3 0.6 V
RPU Internal pullup resistance (EN, SLP_S0#) 250 400 550 kΩ
IIH High-level input current (EN, SLP_S0#) VIN = 3.6 V; MODE != "F"; VIO_SEL = "0" or "R"; -5 5 µA
IIL Low-level input current (EN, SLP_S0#) VIN = GND, VCC = 3.6 V; MODE != "F"; VIO_SEL = "0" or "R"; –11 11 µA
I2C Control Pins (SCL, SDA)
VIH_1p8V High-level input voltage when configured for 1.8V I2C level MODE = "F"; VIO_SEL = "R" or "1"; 1.2 3.6 V
VIL_1p8V Low-level input voltage when configured for 1.8V I2C level MODE = "F"; VIO_SEL = "R" or "1"; -0.3 0.6 V
VIH_3p3V High-level input voltage when configured for 3.3V I2C level MODE = "F"; VIO_SEL = "0" or "F"; 2.0 3.6 V
VIL_3p3V Low-level input voltage when configured for 3.3V I2C level MODE = "F"; VIO_SEL = "0" or "F"; -0.3 0.8 V
VOL Low-level output voltage MODE = "F"; IOL = 6 mA 0 0.4 V
IOL Low-level output current MODE = "F"; VOL = 0.4 V 20 mA
II(I2C) Input current 0.1 × V(I2C) < Input voltage < 3.3 V –1 1 µA
CI(I2C) Input capacitance 10 pF
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz) 150 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400kHz) 150 pF
R(EXT_I2C_FM+) External resistors on both SDA and SCL when operating at FM+ (1MHz) C(I2C_FM+_BUS) = 150 pF 620 820 910 Ω
R(EXT_I2C_FM) External resistors on both SDA and SCL when operating at FM (400 kHz) C(I2C_FM_BUS) = 150 pF 620 1500 2200 Ω