8.6.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
AEQ_STATUS is shown in Table 27.
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This register provides the status of AEQ function.
Table 27. AEQ_STATUS Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-5 |
RESERVED |
R |
0x0 |
Reserved
|
4 |
DONE_STAT |
RH |
0x0 |
This flag is set after DAC wait timer expires.
|
3-0 |
AEQ_STAT |
RH |
0x0 |
Optimal EQ determined by FSM after the completion of Full AEQ. This field will also indicate EQ used for Fast AEQ. This field will include the value programmed into OVER_EQ_CTRL field.
|