8.6.1.4 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
DP23EQ_SEL is shown in Table 16.
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This register controls the receiver equalization setting for the DisplayPort receivers 2 and 3.
Table 16. DP23EQ_SEL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-4 |
DP3EQ_SEL |
RH/W |
0x0 |
Field selects EQ for DP lane 3 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 3 based on value written to this field.
|
3-0 |
DP2EQ_SEL |
RH/W |
0x0 |
Field selects EQ for DP lane 2 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 2 based on value written to this field.
|