SLLSFB2 April   2020 TUSB1146

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematics
  4. 4 Revision History
  5. 5 TUSB1146 Pin Configuration and Functions
    1.     TUSB1146 Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  Control I/O DC Electrical Characteristics
    7. 6.7  USB and DP Electrical Characteristics
    8. 6.8  DCI Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 VOD modes
        1. 8.4.5.1 Linearity VOD
        2. 8.4.5.2 Limited VOD
      6. 8.4.6 Transmit Equalization
      7. 8.4.7 USB3.1 Modes
      8. 8.4.8 Downstream Facing Port Adaptive Equalization
        1. 8.4.8.1 Fast Adaptive Equalization in I2C Mode
        2. 8.4.8.2 Full Adaptive Equalization
    5. 8.5 Programming
      1. 8.5.1 Transition between Modes
      2. 8.5.2 Pseudocode Examples
        1. 8.5.2.1 Fast AEQ with linear redriver mode
        2. 8.5.2.2 Fast AEQ with limited redriver mode
        3. 8.5.2.3 Full AEQ with linear redriver mode
        4. 8.5.2.4 Full AEQ with limited redriver mode
      3. 8.5.3 TUSB1146 I2C Address Options
      4. 8.5.4 TUSB1146 I2C Slave Behavior
    6. 8.6 Register Maps
      1. 8.6.1 TUSB1146 Registers
        1. 8.6.1.1  General_1 Register (Offset = 0xA) [reset = 0x1]
          1. Table 13. General_1 Register Field Descriptions
        2. 8.6.1.2  DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
          1. Table 14. DCI_TXEQ_CTRL Register Field Descriptions
        3. 8.6.1.3  DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
          1. Table 15. DP01EQ_SEL Register Field Descriptions
        4. 8.6.1.4  DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
          1. Table 16. DP23EQ_SEL Register Field Descriptions
        5. 8.6.1.5  DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
          1. Table 17. DisplayPort_1 Register Field Descriptions
        6. 8.6.1.6  DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
          1. Table 18. DisplayPort_2 Register Field Descriptions
        7. 8.6.1.7  AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
          1. Table 19. AEQ_CONTROL1 Register Field Descriptions
        8. 8.6.1.8  AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
          1. Table 20. AEQ_CONTROL2 Register Field Descriptions
        9. 8.6.1.9  AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
          1. Table 21. AEQ_LONG Register Field Descriptions
        10. 8.6.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
          1. Table 22. USBC_EQ Register Field Descriptions
        11. 8.6.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
          1. Table 23. SS_EQ Register Field Descriptions
        12. 8.6.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
          1. Table 24. USB3_MISC Register Field Descriptions
        13. 8.6.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
          1. Table 25. USB_STATUS Register Field Descriptions
        14. 8.6.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
          1. Table 26. VOD_CTRL Register Field Descriptions
        15. 8.6.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
          1. Table 27. AEQ_STATUS Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C receptacle) Configuration
        2. 9.2.2.2 USB Downstream Facing Port (USB-C receptacle to USB Host) Configuration
          1. 9.2.2.2.1 Fixed Equalization
          2. 9.2.2.2.2 Fast Adaptive Equalization
          3. 9.2.2.2.3 Full Adaptive Equalization
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.4 TUSB1146 I2C Slave Behavior

TUSB1146 TUSB1144_I2CWR.gifFigure 29. I2C Write with Data

The following procedure should be followed to write data to TUSB1146 I2C registers (refer to Figure 29):

  1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1146 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1146 acknowledges the address cycle.
  3. The master presents the register offset within TUSB1146 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1146 acknowledges the sub-address cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The TUSB1146 acknowledges the byte transfer
  7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB1146.
  8. The master terminates the write operation by generating a stop condition (P).

TUSB1146 TUSB1144_I2CRD.gifFigure 30. I2C Read without repeated Start

The following procedure should be followed to read the TUSB1146 I2C registers without a repeated Start (refer Figure 30).

  1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1146 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
  2. The TUSB1146 acknowledges the 7-bit address cycle.
  3. Following the acknowledge the master continues sending clock.
  4. The TUSB1146 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I2C register occurred prior to the read, then the TUSB1146 shall start at the register offset specified in the write.
  5. The TUSB1146 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  6. If an ACK is received, the TUSB1146 transmits the next byte of data as long as master provides the clock. If a NAK is received, the TUSB1146 stops providing data and waits for a stop condition (P).
  7. The master terminates the write operation by generating a stop condition (P).

TUSB1146 TUSB1144_I2CST.gifFigure 31. I2C Read with repeated Start

The following procedure should be followed to read the TUSB1146 I2C registers with a repeated Start (refer Figure 31).

  1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1146 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1146 acknowledges the 7-bit address cycle.
  3. The master presents the register offset within TUSB1146 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1146 acknowledges the register offset cycle.
  5. The master presents a repeated start condition (Sr).
  6. The master initiates a read operation by generating a start condition (S), followed by the TUSB1146 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  7. The TUSB1146 acknowledges the 7-bit address cycle.
  8. The TUSB1146 transmit the contents of the memory registers MSB-first starting at the register offset.
  9. The TUSB1146 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  10. If an ACK is received, the TUSB1146 transmits the next byte of data as long as master provides the clock. If a NAK is received, the TUSB1146 stops providing data and waits for a stop condition (P).
  11. The master terminates the read operation by generating a stop condition (P).

TUSB1146 TUSB1144_I2CWR_NDAT.gifFigure 32. I2C Write without data

The following procedure should be followed for setting a starting sub-address for I2C reads (refer to Figure 32).

  1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1146 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB1146 acknowledges the address cycle.
  3. The master presents the register offset within TUSB1146 to be written, consisting of one byte of data, MSB-first.
  4. The TUSB1146 acknowledges the register offset cycle.
  5. The master terminates the write operation by generating a stop condition (P).

NOTE

After initial power-up, if no register offset is included for the read procedure (refer to Figure 30), then reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. During a read operation, the TUSB1146 auto-increments the I2C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C master.