SLLSEL4A September   2014  – October 2014 TUSB1210-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 Power Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Timing Requirements
      1. 6.13.1 Timing Parameter Definitions
      2. 6.13.2 Interface Target Frequencies
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210-Q1 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. 7.5.1  VENDOR_ID_LO
      2. 7.5.2  VENDOR_ID_HI
      3. 7.5.3  PRODUCT_ID_LO
      4. 7.5.4  PRODUCT_ID_HI
      5. 7.5.5  FUNC_CTRL
      6. 7.5.6  FUNC_CTRL_SET
      7. 7.5.7  FUNC_CTRL_CLR
      8. 7.5.8  IFC_CTRL
      9. 7.5.9  IFC_CTRL_SET
      10. 7.5.10 IFC_CTRL_CLR
      11. 7.5.11 OTG_CTRL
      12. 7.5.12 OTG_CTRL_SET
      13. 7.5.13 OTG_CTRL_CLR
      14. 7.5.14 USB_INT_EN_RISE
      15. 7.5.15 USB_INT_EN_RISE_SET
      16. 7.5.16 USB_INT_EN_RISE_CLR
      17. 7.5.17 USB_INT_EN_FALL
      18. 7.5.18 USB_INT_EN_FALL_SET
      19. 7.5.19 USB_INT_EN_FALL_CLR
      20. 7.5.20 USB_INT_STS
      21. 7.5.21 USB_INT_LATCH
      22. 7.5.22 DEBUG
      23. 7.5.23 SCRATCH_REG
      24. 7.5.24 SCRATCH_REG_SET
      25. 7.5.25 SCRATCH_REG_CLR
      26. 7.5.26 VENDOR_SPECIFIC1
      27. 7.5.27 VENDOR_SPECIFIC1_SET
      28. 7.5.28 VENDOR_SPECIFIC1_CLR
      29. 7.5.29 VENDOR_SPECIFIC2
      30. 7.5.30 VENDOR_SPECIFIC2_SET
      31. 7.5.31 VENDOR_SPECIFIC2_CLR
      32. 7.5.32 VENDOR_SPECIFIC1_STS
      33. 7.5.33 VENDOR_SPECIFIC1_LATCH
      34. 7.5.34 VENDOR_SPECIFIC3
      35. 7.5.35 VENDOR_SPECIFIC3_SET
      36. 7.5.36 VENDOR_SPECIFIC3_CLR
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. 9 Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
      1. 11.5.1 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Via Channel
    2. 12.2 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

VBUS, and VBAT, and VDDIO, are needed for power the TUSB1210-Q1. Recommended operation is for VBAT to be present before VDDIO. Applying VDDIO before VBAT to TUSB1210 is not recommended as there is a diode from VDDIO to VBAT which will be forward biased when VDDIO is present but VBAT is not present. TUSB1210-Q1 does not strictly require VBUS to function.

9.1 TUSB1210 Power Supply

  • The VDDIO pins of the TUSB1210-Q1 supply 1.8 V (nominal) power to the core of the TUSB1210-Q1. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The VBAT pin of the TUSB1210-Q1 supply 3.3 V (nominal) power rail to the TUSB1210-Q1. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The VBUS pin of the TUSB1210-Q1 supply 5.0 V (nominal) power rail to the TUSB1210-Q1. This pin is normally connected to the VBUS pin of the USB connector.
  • The VBUS pin of the TUSB1210-Q1 supply 5.0 V (nominal) power rail to the TUSB1210-Q1. This pin is normally connected to the VBUS pin of the USB connector.

9.2 Ground

It is recommended that almost one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. An earth or chassis ground is implemented only near the USB port connectors on a different plane for EMI and ESD purposes.

9.3 Power Providers

Table 13 is a summary of TUSB1210-Q1 power providers.

Table 13. Power Providers(1)

NAME USAGE TYPE TYPICAL
VOLTAGE (V)		 MAXIMUM
CURRENT (mA)
VDD15 Internal LDO 1.5 50
VDD18 External LDO 1.8 30
VDD33 Internal LDO 3.1 15
(1) VDD33 may be supplied externally, or by shorting the VDD33 pin to VBAT pin provided VBAT min is in range [3.2 V : 3.6 V]. Note that the VDD33 LDO will always power-on when the chip is enabled, irrespective of whether VDD33 is supplied externally or not. In the case the VDD33 pin is not supplied externally in the application, the electrical specs for this LDO are provided below.

9.4 Power Modules

9.4.1 VDD33 Regulator

The VDD33 internal LDO regulator powers the USB PHY, charger detection, and OTG functions of the USB subchip inside TUSB1210-Q1. Power Characteristics describes the regulator characteristics.

VDD33 regulator takes its power from VBAT.

Since the USB2.0 standard requires data lines to be biased with pullups biased from a supply greater than 3 V, and since VDD33 regulator has an inherent voltage drop from its input, VBAT, to its regulated output, TUSB1210-Q1 will not meet USB 2.0 Standard if operated from a battery whose voltage is lower than
3.3 V.

9.4.2 VDD18 Supply

The VDD18 supply is powered externally at the VDD18 pin. See Table 11 for external components.

9.4.3 VDD15 Regulator

The VDD15 internal LDO regulator powers the USB subchip inside TUSB1210-Q1. Power Characteristics describes the regulator characteristics.

9.5 Power Consumption

Table 14 describes the power consumption depending on the use cases.

NOTE

The typical power consumption is obtained in the nominal operating conditions and with the TUSB1210-Q1 standalone.

Table 14. Power Consumption

MODE CONDITIONS SUPPLY TYPICAL
CONSUMPTION		 UNIT
OFF Mode VBAT = 3.6 V, VDDIO = 1.8 V, VDD18 = 1.8 V, CS = 0 V IVBAT 8 µA
IVDDIO 3
IVDD18 5
ITOTAL 16
Suspend Mode VBUS = 5 V, VBAT = 3.6 V, VDDIO = 1.8 V, No clock IVBAT 204 µA
IVDDIO 3
IVDD18 3
ITOTAL 210
HS USB Operation
(Synchronous Mode)		 VBAT = 3.6 V, VDDIO = 1.8 V, VDD18 = 1.8 V, active USB transfer IVBAT 24.6 mA
IVDDIO 1.89
IVDD18 21.5
ITOTAL 48
FS USB Operation
(Synchronous Mode)		 VBAT = 3.6 V, VDDIO = 1.8 V, active USB transfer IVBAT 25.8 mA
IVDDIO 1.81
IVDD18 4.06
ITOTAL 31.7
Reset Mode RESETB = 0 V, VBUS = 5 V, VBAT = 3.6 V, VDDIO = 1.8 V, No clock IVBAT 237 µA
IVDDIO 3
IVDD18 3
ITOTAL 243