SLLSE09J November   2009  – July 2021 TUSB1210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 OTG ID Electrical
    12. 6.12 Power Characteristics
    13. 6.13 Switching Characteristics
    14. 6.14 Timing Requirements
      1. 6.14.1 Timing Parameter Definitions
      2. 6.14.2 Interface Target Frequencies
    15. 6.15 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. 7.5.1  VENDOR_ID_LO
      2. 7.5.2  VENDOR_ID_HI
      3. 7.5.3  PRODUCT_ID_LO
      4. 7.5.4  PRODUCT_ID_HI
      5. 7.5.5  FUNC_CTRL
      6. 7.5.6  FUNC_CTRL_SET
      7. 7.5.7  FUNC_CTRL_CLR
      8. 7.5.8  IFC_CTRL
      9. 7.5.9  IFC_CTRL_SET
      10. 7.5.10 IFC_CTRL_CLR
      11. 7.5.11 OTG_CTRL
      12. 7.5.12 OTG_CTRL_SET
      13. 7.5.13 OTG_CTRL_CLR
      14. 7.5.14 USB_INT_EN_RISE
      15. 7.5.15 USB_INT_EN_RISE_SET
      16. 7.5.16 USB_INT_EN_RISE_CLR
      17. 7.5.17 USB_INT_EN_FALL
      18. 7.5.18 USB_INT_EN_FALL_SET
      19. 7.5.19 USB_INT_EN_FALL_CLR
      20. 7.5.20 USB_INT_STS
      21. 7.5.21 USB_INT_LATCH
      22. 7.5.22 DEBUG
      23. 7.5.23 SCRATCH_REG
      24. 7.5.24 SCRATCH_REG_SET
      25. 7.5.25 SCRATCH_REG_CLR
      26. 7.5.26 VENDOR_SPECIFIC1
      27. 7.5.27 VENDOR_SPECIFIC1_SET
      28. 7.5.28 VENDOR_SPECIFIC1_CLR
      29. 7.5.29 VENDOR_SPECIFIC2
      30. 7.5.30 VENDOR_SPECIFIC2_SET
      31. 7.5.31 VENDOR_SPECIFIC2_CLR
      32. 7.5.32 VENDOR_SPECIFIC1_STS
      33. 7.5.33 VENDOR_SPECIFIC1_LATCH
      34. 7.5.34 VENDOR_SPECIFIC3
      35. 7.5.35 VENDOR_SPECIFIC3_SET
      36. 7.5.36 VENDOR_SPECIFIC3_CLR
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. 9 Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations
    2. 10.2 Layout Guidelines
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 PHY Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER COMMENTS MIN TYP MAX UNIT
LS/FS Single-Ended Receivers
USB single-ended receivers
SKWVP_VM Skew between VP and VM Driver outputs unloaded –2 0 2 ns
VSE_HYS Single-ended hysteresis 50  mV
VIH High (driven) 2 V
VIL Low 0.8 V
VTH Switching threshold 0.8 2 V
LS/FS Differential Receiver
VDI Differential input sensitivity Ref. USB2.0 200 mV
VCM Differential Common mode range Ref. USB2.0 0.8  2.5  V
LS Transmitter
VOL Low Ref. USB2.0 0 300 mV
VOH High (driven) Ref. USB2.0 2.8  3.6  V
VCRS Output signal crossover voltage Ref. USB2.0, covered by eye diagram 1.3 2 V
tr Rise time Ref. USB2.0, covered by eye diagram 75 300 ns
tf Fall time 75 300 ns
tFRFM Differential rise and fall time matching 80% 125%
tFDRATE Low-speed data rate Ref. USB2.0, covered by eye diagram 1.4775 1.5225 Mb/s
tDJ1 Source jitter total (including frequency tolerance) To next transition Ref. USB2.0, covered by eye diagram –25 25 ns
tDJ2 For paired transitions –10 10
tFEOPT Source SE0 interval of EOP Ref. USB2.0, covered by eye diagram 1.25 1.5 µs
Downstream eye diagram Ref. USB2.0, covered by eye diagram
VCM Differential common mode range Ref. USB2.0 0.8 2.5 V
FS Transmitter
VOL Low Ref. USB2.0 0 300 mV
VOH High (driven) Ref. USB2.0 2.8  3.6  V
VCRS Output signal crossover voltage Ref. USB2.0, covered by eye diagram 1.3 2 V
tFR Rise time Ref. USB2.0 4 20 ns
tFF Fall time Ref. USB2.0 4 20 ns
tFRFM Differential rise and fall time matching Ref. USB2.0, covered by eye diagram 90% 111.11%
ZDRV Driver output resistance Ref. USB2.0 28 44 Ω
TFDRATE Full-speed data rate Ref. USB2.0, covered by eye diagram 11.97 12.03 Mb/s
tDJ1 Source jitter total (including frequency tolerance) To next transition Ref. USB2.0, covered by eye diagram –2 2 ns
tDJ2 For paired transitions –1 1
TFEOPT Source SE0 interval of EOP Ref. USB2.0, covered by eye diagram 160 175 ns
Downstream eye diagram Ref. USB2.0, covered by eye diagram
Upstream eye diagram
HS Differential Receiver
VHSSQ High-speed squelch detection threshold (differential signal amplitude) Ref. USB2.0 100 150 mV
VHSDSC High-speed disconnect detection threshold (differential signal amplitude) Ref. USB2.0 525  625  mV
High-speed differential input signaling levels Ref. USB2.0, specified by eye pattern templates mV
VHSCM High-speed data signaling common mode voltage range (guidelines for receiver) Ref. USB2.0 –50 500 mV
Receiver jitter tolerance Ref. USB2.0, specified by eye pattern templates 150 ps
HS Transmitter
VHSOI High-speed idle level Ref. USB2.0 –10 10 mV
VHSOH High-speed data signaling high Ref. USB2.0 360 440 mV
VHSOL High-speed data signaling low Ref. USB2.0 –10 10 mV
VCHIRPJ Chirp J level (differential voltage) Ref. USB2.0 700 1100 mV
VCHIRPK Chirp K level (differential voltage) Ref. USB2.0 -900 -500 mV
tr Rise Time (10% - 90%) Ref. USB2.0, covered by eye diagram 500 ps
tf Fall time (10% - 90%) Ref. USB2.0, covered by eye diagram 500 ps
ZHSDRV Driver output resistance (which also serves as high-speed termination) Ref. USB2.0 40.5 49.5 Ω
THSDRAT High-speed data range Ref. USB2.0, covered by eye diagram 479.76 480.24 Mb/s
Data source jitter Ref. USB2.0, covered by eye diagram
Downstream eye diagram Ref. USB2.0, covered by eye diagram
Upstream eye diagram Ref. USB2.0, covered by eye diagram
CEA-2011/UART Transceiver
UART Transmitter CEA-2011
tPH_UART_EDGE Phone UART edge rates DP_PULLDOWN asserted 1 Μs
VOH_SER Serial interface output high ISOURCE = 4 mA 2.4 3.3 3.6 V
VOL_SER Serial interface output low ISINK = –4 mA 0 0.1 0.4 V
UART Receiver CEA-2011
VIH_SER  Serial interface input high DP_PULLDOWN asserted 2 V
VIL_SER Serial interface input low DP_PULLDOWN asserted 0.8 V
VTH Switching threshold 0.8 2 V