SLLSE09J November   2009  – July 2021 TUSB1210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 OTG ID Electrical
    12. 6.12 Power Characteristics
    13. 6.13 Switching Characteristics
    14. 6.14 Timing Requirements
      1. 6.14.1 Timing Parameter Definitions
      2. 6.14.2 Interface Target Frequencies
    15. 6.15 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. 7.5.1  VENDOR_ID_LO
      2. 7.5.2  VENDOR_ID_HI
      3. 7.5.3  PRODUCT_ID_LO
      4. 7.5.4  PRODUCT_ID_HI
      5. 7.5.5  FUNC_CTRL
      6. 7.5.6  FUNC_CTRL_SET
      7. 7.5.7  FUNC_CTRL_CLR
      8. 7.5.8  IFC_CTRL
      9. 7.5.9  IFC_CTRL_SET
      10. 7.5.10 IFC_CTRL_CLR
      11. 7.5.11 OTG_CTRL
      12. 7.5.12 OTG_CTRL_SET
      13. 7.5.13 OTG_CTRL_CLR
      14. 7.5.14 USB_INT_EN_RISE
      15. 7.5.15 USB_INT_EN_RISE_SET
      16. 7.5.16 USB_INT_EN_RISE_CLR
      17. 7.5.17 USB_INT_EN_FALL
      18. 7.5.18 USB_INT_EN_FALL_SET
      19. 7.5.19 USB_INT_EN_FALL_CLR
      20. 7.5.20 USB_INT_STS
      21. 7.5.21 USB_INT_LATCH
      22. 7.5.22 DEBUG
      23. 7.5.23 SCRATCH_REG
      24. 7.5.24 SCRATCH_REG_SET
      25. 7.5.25 SCRATCH_REG_CLR
      26. 7.5.26 VENDOR_SPECIFIC1
      27. 7.5.27 VENDOR_SPECIFIC1_SET
      28. 7.5.28 VENDOR_SPECIFIC1_CLR
      29. 7.5.29 VENDOR_SPECIFIC2
      30. 7.5.30 VENDOR_SPECIFIC2_SET
      31. 7.5.31 VENDOR_SPECIFIC2_CLR
      32. 7.5.32 VENDOR_SPECIFIC1_STS
      33. 7.5.33 VENDOR_SPECIFIC1_LATCH
      34. 7.5.34 VENDOR_SPECIFIC3
      35. 7.5.35 VENDOR_SPECIFIC3_SET
      36. 7.5.36 VENDOR_SPECIFIC3_CLR
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. 9 Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations
    2. 10.2 Layout Guidelines
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations

Table 10-1 TUSB121x USB2.0 Product Family Board Layout Recommendations
ItemUSB General Considerations
1.00USB design requires symmetrical termination and symmetrical component placement along the DP and DM paths.
1.01Place the USB host controller and major components on the unrouted board first.
1.02Place the USB host controller, as close as possible to the transceiver device, that is, ULPI interface traces as short as possible.
1.03Route high-speed clock and high-speed USB. Route differential pairs first.
Since these signals are critical and long length traces are to be avoided, it is therefore recommended to route DP/DM before routing less critical signals on the board. A similar recommendation is true for CLK, and ULPI signals which should be routed with equalized trace length.
1.04Maintain maximum possible distance between high-speed clocks/periodic signals to high speed USB differential pairs and any connector leaving the PCB (such as I/O connectors, control, and signal headers or power connectors).
1.05Place the USB receptacle at the board edge.
1.06Maximum TI-recommended external capacitance on DP (or DM) lines is 4 pF
  • This capacitance is the sum of all external discrete components, that is, the total capacitance on DP (or DM) lines including trace capacitance can be larger than 4 pF.
  • All discrete components should be placed as close as possible to the USB receptacle.
1.07Place the low-capacitance ESD protections as close as possible to the USB receptacle, with no other external devices in between.
1.08Common mode chokes degrade signal quality, thus they should only be used if EMI performance enhancement is absolutely necessary.
1.09Place the common mode choke (if required to improve EMI performance) as close as possible to the USB receptacle (but after one or more of the ESD devices).
USB Interface (DP, DM)
2.00Separate signal traces into similar categories and route similar signal traces together, that is, DP/DM and ULPI.
2.01Route the USB receptacle ground pin to the analog ground plane of the device with multiple via connections.
2.02Route the DP/DM trace pair together.
2.03For HS-capable devices, route the DP/DM signals from the device to the USB receptacle with an optimum trace length of 5 cm. Maximum trace length 1-way delay of 0.5 ns (7.5 cm for 67 ps/cm in FR-3).
2.04Match the DP/DM trace lengths. Maximum mismatch allowable is 150 mils (≈0.4 cm).
2.05Route the DP/DM signals with 90 Ω differential impedance, and 22.5≈30-Ω common-mode impedance (objective is to have Zodd ≈ Z0 = Zdiff/2 = 45 Ω).
2.06Use an impedance calculator to determine the trace width and spacing required for the specific board stack up being used.
2.07Keep the maximum possible distance between DP and DM signals from the other platform clocks, power sources and digital or analog signals.
2.08Do not route DP/DM signals over or under crystals, oscillators, clock synthesizers, magnetic devices, or ICs that use clocks.
2.09Avoid changing the routing layer for DP/DM traces. If unavoidable, use multiple vias.
2.10Minimize bends and corners on DP/DM traces.
2.11When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal by minimizing impedance discontinuities.
2.12Avoid creating stubs on the DP/DM traces as stubs cause signal reflections and affect global signal quality.
2.13If stubs are unavoidable, they must be less than 200 mils (≈0.5 cm).
2.14Route DP/DM signals over continuous VCC or GND planes, without interruption, avoiding crossing anti-etch (plane splits), which increase both inductance and radiation levels by introducing a greater loop area.
2.15Route DP/DM signals with at least 25 mils (≈0.65 mm) away from any plane splits.
2.16Follow the 20×h thumb rule by keeping traces at least 20×(height above the plane) away from the edge of the plane (VCC or GND, depending on the plane the trace is over).
2.17Changing signal layers is preferable to crossing plane splits if a choice must be made.
2.18If crossing a plane split is completely unavoidable, proper placement of stitching capacitors can minimize the adverse effects on EMI and signal quality performance caused by crossing the split.
2.19Avoid anti-etch on the ground plane.
ULPI Interface (ULPIDATA<7:0>, ULPICLK, ULPINXT, ULPIDIR, ULPISTP)
3.00Route ULPI 12-pin bus as a 50 Ω single-ended adapted bus.
3.01Route ULPI 12-pin bus with minimum trace lengths and a strict maximum of 90 mm, to ensure timing. (Timing budget 600 ps maximum 1-way delay assuming 66 ps/cm.)
3.02Route ULPI 21-pin bus equalizing paths lengths as much as possible to have equal delays.
3.03Route ULPI 12-pin bus as clock signals and set a minimum spacing of 3 times the trace width (S < 3W).
3.04If the 3W minimum spacing is not respected, the minimum spacing for clock signals based on EMI testing experience is 50 mils (1.27 mm).
3.05Route ULPI 12-pin bus with a dedicated ground plane.
3.06Place and route the ULPI monitoring buffers as close as possible from the device ULPI bus (on test boards).
USB Clock (USBCLKIN, CLK_IN1, CLK_IN0)
4.00Route the USB clock with the minimum possible trace length.
4.01Keep the maximum possible distance between the USB clock and the other platform clocks, power sources, and digital and analog signals.
4.02Route the USBCLKIN, CLK_IN1 and CLK_IN0 inputs as 50 Ω single-ended signals.
USB Power Supply (VBUS, REG3V3, REG1V5, VBAT)
5.00VBUS must be a power plane from the device VBUS ball to the USB receptacle, or if a power plan is not possible, VBUS must be as large as possible.
5.01Power signals must be wide to accommodate current level.