SLLSE32G November   2010  – November 2017 TUSB1310A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
    2. 3.2 Configuration Pins
    3. 3.3 Signal Descriptions
      1. 3.3.1 PIPE
      2. 3.3.2 ULPI
      3. 3.3.3 Clocking
      4. 3.3.4 JTAG Interface
      5. 3.3.5 Reset and Output Control Interface
      6. 3.3.6 Strap Options
      7. 3.3.7 USB Interfaces
      8. 3.3.8 Special Connect
      9. 3.3.9 Power and Ground
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Device Power-Consumption Summary
    5. 4.5 DC Characteristics for 1.8-V Digital I/O
    6. 4.6 Thermal Characteristics
    7. 4.7 Timing Characteristics
      1. 4.7.1 Power-Up and Reset Timing
      2. 4.7.2 PIPE Transmit
      3. 4.7.3 PIPE Receive
      4. 4.7.4 ULPI Parameters
      5. 4.7.5 ULPI Clock
      6. 4.7.6 ULPI Transmit
      7. 4.7.7 ULPI Receive Timing
    8. 4.8 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Power On and Reset
        1. 5.3.1.1 RESETN and PHY_RESETN: Hardware Reset
        2. 5.3.1.2 ULPI Reset: Software Reset
        3. 5.3.1.3 OUT_ENABLE: Output Enable
        4. 5.3.1.4 Power-Up Sequence
      2. 5.3.2 Clocks
        1. 5.3.2.1 Clock Distribution
        2. 5.3.2.2 Output Clock
      3. 5.3.3 Power State Transition Time
      4. 5.3.4 Power Management
        1. 5.3.4.1 USB Power Management
      5. 5.3.5 Receiver Status
        1. 5.3.5.1 Clock Tolerance Compensation
        2. 5.3.5.2 Receiver Detection
        3. 5.3.5.3 8b/10b Decode Errors
        4. 5.3.5.4 Elastic Buffer Errors
        5. 5.3.5.5 Disparity Errors
      6. 5.3.6 Loopback
      7. 5.3.7 Adaptive Equalizer
    4. 5.4 Device Functional Modes
      1. 5.4.1 USB 3.0 Mode
      2. 5.4.2 USB 2.0 Mode
      3. 5.4.3 ULPI Modes
    5. 5.5 Register Maps
      1. 5.5.1  Vendor ID and Product ID (00h-03h)
      2. 5.5.2  Function Control (04h-06h)
      3. 5.5.3  Interface Control (07h-09h)
      4. 5.5.4  OTG Control
      5. 5.5.5  USB Interrupt Enable Rising (0Dh-0Fh)
      6. 5.5.6  USB Interrupt Enable Falling (10h-12h)
      7. 5.5.7  USB Interrupt Status (13h)
      8. 5.5.8  USB Interrupt Latch (14h)
      9. 5.5.9  Debug (15h)
      10. 5.5.10 Scratch Register (16-18h)
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 Clock Source Requirements
          1. 6.2.1.1.1 Clock Source Selection Guide
          2. 6.2.1.1.2 Oscillator
          3. 6.2.1.1.3 Crystal
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Chip Connection on PCB
          1. 6.2.2.1.1 USB Connector Pins Connection
          2. 6.2.2.1.2 Clock Connections
      3. 6.2.3 Application Curve
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
          1. 6.2.4.1.1 High-Speed Differential Routing
          2. 6.2.4.1.2 SuperSpeed Differential Routing
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Recommendations
      1. 6.3.1 1.1-V and 1.8-V Digital Supply
      2. 6.3.2 1.1-V, 1.8-V and 3.3-V Analog Supplies
      3. 6.3.3 Capacitor Selection Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Universal Serial Bus (USB)
    • Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver
      • One 5.0-Gbps SuperSpeed Connection
      • One 480-Mbps HS/FS/LS Connection
    • Fully Compliant With USB 3.0 Specification, Revision 1.0
    • Supports 3+ Meters USB 3.0 Cable Length
    • Fully Adaptive Equalizer to Optimize Receiver Sensitivity
    • PIPE to Link-Layer Controller
      • Supports 16-Bit SDR Mode at 250 MHz
      • Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0
    • ULPI to Link-Layer Controller
      • Supports 8-Bit SDR Mode at 60 MHz
      • Supports Synchronous Mode and Low-Power Mode
      • Compliant With UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
  • General Features
    • IEEE 1149.1 JTAG Support
    • IEEE 1149.6 JTAG support for the SuperSpeed Port
    • Operates on One Reference Clock of 40 MHz
    • 3.3-, 1.8-, and 1.1-V Supply Voltages
    • 1.8-V PIPE and ULPI I/O
    • Available in Lead-Free 175-Ball 12- × 12-nF NFBGA Package (ZAY)

1.2 Applications

  • Surveillance Cameras
  • Digital Still Cameras
  • Multimedia Handsets
  • Phones and Smartphones
  • Portable Media Players
  • Personal Navigation Devices
  • Audio Docks
  • Video- and Wireless-IP Phones
  • Software Defined Radios

1.3 Description

The TUSB1310A device is one port, 5.0-Gbps USB 3.0 physical layer transceiver that operates off of one reference clock, which is provided by either a crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A device provides the clock to the USB controller. The use of one reference clock allows the TUSB1310A device to provide a cost-effective USB 3.0 solution with few external components and a low implementation cost.

The USB controller interfaces to the TUSB1310A device through a PIPE (SuperSpeed) and a ULPI (USB 2.0) interface. The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations with a 60-MHz interface clock.

USB 3.0 reduces active and idle power consumption with improved power-management features. The low-power states of the TUSB1310A device are controlled by the USB controller through the PIPE interface.

SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0 based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TUSB1310A NFBGA (175) 12.00 mm × 12.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.

1.4 Functional Block Diagram

TUSB1310A fbd_sllse32.gif Figure 1-1 Functional Block Diagram