The TUSB1310A device is one port, 5.0-Gbps USB 3.0 physical layer transceiver that operates off of one reference clock, which is provided by either a crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A device provides the clock to the USB controller. The use of one reference clock allows the TUSB1310A device to provide a cost-effective USB 3.0 solution with few external components and a low implementation cost.
The USB controller interfaces to the TUSB1310A device through a PIPE (SuperSpeed) and a ULPI (USB 2.0) interface. The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations with a 60-MHz interface clock.
USB 3.0 reduces active and idle power consumption with improved power-management features. The low-power states of the TUSB1310A device are controlled by the USB controller through the PIPE interface.
SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0 based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TUSB1310A | NFBGA (175) | 12.00 mm × 12.00 mm |
Changes from F Revision (August 2015) to G Revision
Changes from E Revision (July 2012) to F Revision
Figure 3-1 shows the 175-pin ZAY plastic ball grid array (NFBGA) pin assignments.
TYPE | DESCRIPTION |
---|---|
I | Input |
O | Output |
I/O | Input/output |
PD, PU | Internal pullup, internal pulldown |
S | Strapping pin |
P | Power supply |
G | Ground |
The configuration pins are not latched by RESETN.
SIGNAL NAME | TYPE | PIN NO. | MODE NAME | DESCRIPTION |
---|---|---|---|---|
PHY_MODE1 | I, PD | H12 | USB | Must be set to 0. Operates as USB 3.0 transceiver. |
PHY_MODE0 | I, PU | J12 | USB | Must be set to 1. Operates as USB 3.0 transceiver. |
The TUSB1310A supports 16-bit SDR mode with a 250-MHz clock.
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION | ||||||
---|---|---|---|---|---|---|---|---|---|
TX_CLK | I | K1 | TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is the same as PCLK frequency. The rising edge of the clock is the reference for all signals. | ||||||
TX_DATA15 | I | G2 | Parallel USB SuperSpeed data input bus. The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to be transmitted, and TX_DATA15-8 is the second symbol. |
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TX_DATA14 | H2 | ||||||||
TX_DATA13 | H1 | ||||||||
TX_DATA12 | J2 | ||||||||
TX_DATA11 | L3 | ||||||||
TX_DATA10 | L2 | ||||||||
TX_DATA9 | M2 | ||||||||
TX_DATA8 | M1 | ||||||||
TX_DATA7 | N1 | ||||||||
TX_DATA6 | P1 | ||||||||
TX_DATA5 | N2 | ||||||||
TX_DATA4 | P2 | ||||||||
TX_DATA3 | N3 | ||||||||
TX_DATA2 | P3 | ||||||||
TX_DATA1 | N4 | ||||||||
TX_DATA0 | P5 | ||||||||
TX_DATAK1 | I | G1 | Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of TX_DATA, TX_DATAK1 to the upper byte. | ||||||
TX_DATAK0 | J1 | ||||||||
PCLK | O | A6 | Parallel interface data clock. All data movement across the parallel PIPE is synchronous to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference for all signals. | ||||||
RX_DATA15 | O | B9 | Parallel USB SuperSpeed data output bus. The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol received, and RX_DATA15-8 is the second. |
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RX_DATA14 | A9 | ||||||||
RX_DATA13 | A8 | ||||||||
RX_DATA12 | B8 | ||||||||
RX_DATA11 | B5 | ||||||||
RX_DATA10 | B4 | ||||||||
RX_DATA9 | A4 | ||||||||
RX_DATA8 | B3 | ||||||||
RX_DATA7 | A3 | ||||||||
RX_DATA6 | A2 | ||||||||
RX_DATA5 | B1 | ||||||||
RX_DATA4 | C2 | ||||||||
RX_DATA3 | C1 | ||||||||
RX_DATA2 | D1 | ||||||||
RX_DATA1 | D2 | ||||||||
RX_DATA0 | E2 | ||||||||
RX_DATAK1 | O | B7 | Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value of 1 indicates a control byte. | ||||||
RX_DATAK0 | A7 | ||||||||
RX_VALID | O | F1 | Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK. | ||||||
CONTROL AND STATUS SIGNALS | |||||||||
PHY_RESETN | I, PU | J3 | Active Low. Resets the transmitter and receiver. This signal is asynchronous. | ||||||
TX_DETRX_LPBK | I, PD | M6 | Active High. Used to tell the PHY to begin a receiver detection operation or to begin loopback. | ||||||
TX_ELECIDLE | I | K3 | Active High. Forces TX output to electrical idle depending on the power state. | ||||||
RX_ELECIDLE | S, I/O, PD | F3 | Active High. While deasserted with the PHY in P0, P1, P2, or P3, indicates detection of LFPS. | ||||||
RX_STATUS2 | O | C7 | Encodes receiver status and error codes for the received data stream when receiving data. | ||||||
RX_STATUS1 | C6 | BIT 2 | BIT 1 | BIT 0 | DESCRIPTION | ||||
RX_STATUS0 | C5 | 0 | 0 | 0 | Received data OK | ||||
0 | 0 | 1 | 1 SKP ordered set added | ||||||
0 | 1 | 0 | 1 SKP ordered set removed | ||||||
0 | 1 | 1 | Receiver detected | ||||||
1 | 0 | 0 | 8B/10B decode error | ||||||
1 | 0 | 1 | Elastic buffer overflow | ||||||
1 | 1 | 0 | Elastic buffer underflow. This error code is not used if the elasticity buffer is operating in the nominal buffer empty mode. |
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1 | 1 | 1 | Receive disparity error | ||||||
POWER_DOWN1 | I | G3 | Power up and down the transceiver power states. | ||||||
POWER_DOWN0 | H3 | BIT 1 | BIT 0 | DESCRIPTION | |||||
0 | 0 | P0, normal operation | |||||||
0 | 1 | P1, low recovery time latency, power saving state | |||||||
1 | 0 | P2, longer recovery time latency, low-power state | |||||||
1 | 1 | P3, lowest power state | |||||||
When transitioning from P3 to P0, the signaling is asynchronous. | |||||||||
PHY_STATUS | S, I/O, PD | E3 | Active High. Used to communicate completion of several PHY functions including power management state transitions, rate change, and receiver detection. When this signal transitions during entry and exit from P3 and PCLK is not running, then the signaling is asynchronous. | ||||||
PWRPRESENT | O | H11 | Indicates the presence of VBUS | ||||||
CONFIGURATION PINS | |||||||||
TX_ONESZEROS | I, PD | M4 | Active High. Used only when transmitting USB compliance pat-terns CP7 or CP8. Causes the transmitter to transmit an alternating sequence of 50 to 250 ones and 50 to 250 zeros—regardless of the state of the TX_DATA interface. | ||||||
TX_DEEMPH1 | I, PD, PU | K11 | Selects transmitter de-emphasis. When the MAC changes, the TUSB1310A starts to transmit with the new setting within 128 ns. | ||||||
TX_DEEMPH0 | L11 | BIT 1 | BIT 0 | DESCRIPTION | |||||
0 | 0 | –6-dB de-emphasis | |||||||
0 | 1 | –3.5-dB de-emphasis | |||||||
1 | 0 | No de-emphasis | |||||||
1 | 1 | Reserved | |||||||
TX_MARGIN2 | I, PD | M11 | Selects transmitter voltage levels | ||||||
TX_MARGIN1 | M10 | BIT 2 | BIT 1 | BIT 0 | TX_SWING | DESCRIPTION | |||
TX_MARGIN0 | M9 | 0 | 0 | 0 | 0 | Normal operating range 800 mV to 1200 mV |
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0 | 0 | 0 | 1 | Normal operating range 400 mV to 700 mV |
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0 | 0 | 1 | 0 | 800 mV to 1200 mV | |||||
1 | 400 mV to 700 mV | ||||||||
0 | 1 | 0 | 0 | 700 mV to 900 mV | |||||
1 | 300 mV to 500 mV | ||||||||
0 | 1 | 1 | 0 | 400 mV to 600 mV | |||||
1 | 200 mV to 400 mV | ||||||||
1 | Don't care | 0 | 200 mV to 400 mV | ||||||
1 | 1 | 100 mV to 200 mV | |||||||
TX_SWING | I, PD | M5 | Controls transmitter voltage swing level 0: Full swing 1: Half swing |
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RX_POLARITY | I, PD | C8 | Active High. Tells PHY to do a polarity inversion on the received data. Inverted data show up on RX_DATA15-0 within 20 PCLK clocks after RX_POLARITY is asserted. 0: PHY does no polarity inversion 1: PHY does polarity inversion |
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RX_TERMINATION | I, PD | D3 | Controls presence of receiver terminations 0: Terminations removed 1: Terminations present |
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RATE | I, PU | L6 | Controls the link signaling rate The RATE is always 1 |
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ELAS_BUF_MODE | I, PD | C9 | Selects elasticity buffer operating mode 0: Nominal half full buffer mode 1: Nominal empty buffer mode |
The ULPI (ultra low pin count interface) is a low pin count USB PHY to a Link-Layer Controller interface. The ULPI consists of the interface and the ULPI registers. The TUSB1310A device is always the master of the ULPI bus.
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION | |
---|---|---|---|---|
ULPI_CLK | O | P11 | 60-MHz interface clock. All ULPI signals are synchronous to ULPI_CLK. The ULPI_CLK is always a 60-MHz output of the TUSB1310A device. In low-power mode, the ULPI_CLK is not driven. | |
ULPI_DATA7 | S, I/O, PD | N6 | Data bus. Driven to 00h by the Link when the ULPI bus is idle. 8-bit data timed on rising edge of ULPI_CLK |
|
ULPI_DATA6 | P6 | |||
ULPI_DATA5 | N7 | |||
ULPI_DATA4 | P7 | |||
ULPI_DATA3 | N8 | |||
ULPI_DATA2 | P8 | |||
ULPI_DATA1 | P9 | |||
ULPI_DATA0 | N9 | |||
ULPI_DIR | O | M7 | Controls the direction of the ULPI_DATA bus 0: ULPI_DATA lines are inputs 1: ULPI_DATA lines are outputs |
|
ULPI_STP | S, I, PU | M8 | Active High. The Link must assert ULPI_STP to signal the end of a USB transmit packet or a register write operation. The ULPI_STP signal must be asserted in the cycle after the last data byte is presented on the bus. The ULPI_STP has an internal weak pullup to safeguard against false commands on the ULPI_DATA lines. | |
ULPI_NXT | O | N11 | Active High. The PHY asserts ULPI_NXT to throttle all data types, except register read data and the RX CMD. The PHY also asserts ULPI_NXT and ULPI_DIR simultaneously to indicate USB receive activity, if ULPI_DIR was previously low. The PHY is not allowed to assert ULPI_NXT during the first cycle of the TX CMD driven by the Link. |
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION |
---|---|---|---|
XI | I | A12 | Crystal Input. This pin is the clock reference input for the TUSB1310A. The TUSB1310A device supports either a crystal unit, or a 1.8-V clock input. Frequencies supported are 20, 25, 30, or 40 MHz. |
XO | O | A11 | Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open. |
CLKOUT | O | D10 | OOBCLK is driven in U3 mode. |
The JTAG Interface is used for board-level boundary scan. All digital IO support IEEE1149.1 boundary scan and SuperSpeed differential pairs support IEEE1149.6 boundary scan.
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION |
---|---|---|---|
JTAG_TCK | I, PU | G11 | JTAG test clock |
JTAG_TMS | I, PU | D11 | JTAG test mode select |
JTAG_TDI | I, PU | E11 | JTAG test data input |
JTAG_TRSTN | I, PD | E12 | JTAG test asynchronous reset. Active Low. An external pulldown is required for normal operation. |
JTAG_TDO | O | F11 | JTAG test data output |
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION |
---|---|---|---|
RESETN | I | J11 | Active Low. Resets the transmitter and receiver. This signal is asynchronous. |
OUT_ENABLE | I | L10 | Active High. This can be connected to a 1.8-V power-on-reset signal on the PCB to avoid static current and signal contention during power up. 0: Disable all driver outputs while I/O powers are supplied, but internal control circuit powers are not present during power up. 1: Enable all driver outputs during normal operation. |
Strapping pins are latched by reset deassertion in the TUSB1310A device.
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION | ||
---|---|---|---|---|---|
XTAL_DIS (RX_ELECIDLE) |
S, I/O, PD | F3 | Selects an input clock source 0: Crystal Input 1: Clock Input |
||
SSC_DIS (TX_MARGIN0) |
S, I, PD | M9 | Spread spectrum clocking disable 0: SSC enable 1: SSC disable |
||
PIPE_16BIT (PHY_STATUS) |
S, I/O, PD | E3 | Selects PIPE 0: 16-bit PIPE SDR mode Must be 0 at reset. |
||
ISO_START (ULPI_DATA7) |
S, I/O, PD | N6 | Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310A device does not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents a high impedance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs. When in the isolate mode, the TUSB1310A device continues to respond to ULPI. When the isolate mode bit in ULPI register is cleared, the USB interfaces starts transmitting packet data on TX_DATA15-0 and driving PCLK, RX_DATA15-0, RX_DATA1-0, and RX_VALID. | ||
ULPI_8BIT (ULPI_DATA6) |
S, I/O, PD | P6 | Selects ULPI data bus bit width 0: 8-bit ULPI SDR mode Must be set to 0. |
||
REFCLKSEL1, REFCLKSEL0 (ULPI_DATA5, ULPI_DATA4) |
S, I/O, PD | N7 P7 |
Select input reference clock frequency for on-chip oscillator 00: 20 MHz on XI 01: 25 MHz on XI 10: 30 MHz on XI 11: 40 MHz on XI |
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION |
---|---|---|---|
SSTXP | O | H14 | USB SuperSpeed transmitter differential pair |
SSTXM | J14 | ||
SSRXP | I | E14 | USB SuperSpeed receiver differential pair |
SSRXM | F14 | ||
DP | I/O | P14 | USB non-SuperSpeed differential pair |
DM | P13 | ||
VBUS | I | N12 | USB VBUS pin Connected through an external voltage divider |
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION |
---|---|---|---|
R1EXT | O | L14 | High precision external resistor used for calibration. The R1 value shall be 10 kΩ ±1% accuracy. |
R1EXTRTN | I | L13 | R1 ground reference. This pin is not connected to board ground. |
VDDA1P1 | P | M14 | Needs a 1-µF bypass capacitor |
RSVD | I/O | D6 | Must be left open. |
D5 | |||
C13 | |||
C14 | |||
K4 | |||
J4 | |||
A14 |
SIGNAL NAME | TYPE | BALL NO. | DESCRIPTION | |
---|---|---|---|---|
VDDA3P3 | P | P12 | Analog 3.3-V power supply | |
VDDA1P8 | P | N14 | Analog 1.8-V power supply | |
A13 | ||||
C10 | ||||
VDDA1P1 | P | C12 | Analog 1.1-V power supply | |
K14 | ||||
G13 | ||||
G14 | ||||
D14 | ||||
C11 | ||||
VDD1P8 | P | B2 | C3 | Digital IO 1.8-V power supply |
D4 | D7 | |||
D8 | D9 | |||
E4 | F4 | |||
G4 | H4 | |||
L5 | L4 | |||
M3 | L7 | |||
L8 | L9 | |||
VDD1P1 | P | A5 | A10 | Digital 1.1-V power supply |
B6 | B10 | |||
E1 | F2 | |||
K2 | L1 | |||
N5 | P4 | |||
N10 | P10 | |||
K13 | D13 | |||
C4 | ||||
VSSA | G | B14 | B13 | Analog ground |
J13 | H13 | |||
F13 | E13 | |||
K12 | L12 | |||
G12 | ||||
D12 | ||||
N13 | ||||
M12 | ||||
M13 | ||||
VSSOSC | G | B12 | Oscillator ground If using a crystal, this must not be connected to PCB ground plane. See Section 6.2.2 for guidelines. If using an oscillator, this must be connected to PCB ground. |
|
VSS | G | F6 | F7 | Digital ground |
F8 | F9 | |||
G6 | G7 | |||
G8 | G9 | |||
J6 | J7 | |||
H6 | H7 | |||
H8 | H9 | |||
J8 | J9 | |||
B11 | F12 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD1P1 steady-state supply voltage | –0.3 | 1.4 | V | |
VDD1P8 steady-state supply voltage | –0.3 | 2.45 | V | |
VDDA1P1 steady-state supply voltage | –0.3 | 1.4 | V | |
VDDA1P8 steady-state supply voltage | –0.3 | 2.45 | V | |
VDDA3P3 steady-state supply voltage | –0.3 | 3.8 | V | |
Storage temperature | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
VDDA3P3 power consumption | 13 | mW | |||
VDDA1P8 power consumption | 77 | mW | |||
VDDA1P1 power consumption | 118 | mW | |||
VDD1P1 power consumption | 98 | mW | |||
VDD1P8 power consumption | 128 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | High-level input voltage | 0.65 VDDS | V | |||
VIL | Low-level input voltage | 0.35 VDDS | V | |||
VOH | High-level output voltage | IO = –2 mA, VDDS = 1.62 V to 1.98 V, driver enabled, pullup or pulldown disabled |
VDDS – 0.45 | V | ||
IO = –2 mA, VDDS = 1.4 V to 1.6 V, driver enabled, pullup or pulldown disabled |
0.75 VDDS | |||||
VOL | Low-level output voltage | IO = 2 mA, VDDS = 1.62 V to 1.98 V, driver enabled, pullup or pulldown disabled |
0.45 | V | ||
IO = 2 mA, VDDS = 1.4 V to 1.6 V, driver enabled, pullup or pulldown disabled |
0.25 VDDS | |||||
Vhys | Input hysteresis | 100 | 270 | mV | ||
II | Input current | Any receiver, including those with a pullup or pulldown. The pullup or pulldown must be disabled. | ±1 | µA | ||
II(PUon) | Input current with pullup enabled | Receiver pullup only, pullup enabled (not inhibited), VPAD = 0 V |
–47 to –169 | µA | ||
Receiver pullup only, pullup enabled (not inhibited) | –100 | |||||
IOZ | Off-state output current | Driver only, driver disabled | ±20 | µA | ||
IZ | Total leakage current(1) | ±20 | µA | |||
VTX_DIFF_SS | SSTXP, SSTXN differential p-p TX voltage swing | 0.8 | 1.2 | V | ||
RTX_DIFF_DC | DC differential impedance | 72 | 120 | Ω | ||
VTX_RCV_DET | The amount of voltage change allowed during receiver detection | 0.6 | V | |||
CAC_COUPLING | AC coupling capacitor | 75 | 200 | nF | ||
RRX_DC | Receiver DC common-mode impedance | 18 | 30 | Ω | ||
RRX_DIFF_DC | DC differential impedance | 72 | 120 | Ω | ||
VRX_LFPS_DET | LFPS detect threshold | 100 | 300 | mV | ||
VCM_AC_LFPS | LFPS common-mode voltage | 100 | mV | |||
VCM_LFPS_active | LFPS common-mode voltage active | 10 | mV | |||
VTX_DIFF_PP_LFPS | LFPS differential voltage | 800 | 1200 | mV |
THERMAL METRIC(1) | TUSB1310A | UNIT | |
---|---|---|---|
ZAY (NFBGA) | |||
175 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 34.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 21 | °C/W |
RθJB | Junction-to-board thermal resistance | 18.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 17.5 | °C/W |
The TUSB1310A device does not drive signals on any strapping pins before they are latched internally.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Tcfgin1 | Hardware configuration latch-in time from RESETN | 0 | ns | ||
Tcfgin2 | Time from RESETN to driver outputs on strapping pins | 0 | ns | ||
RESETN pulse width | 1 | µs | |||
RESETN to PHY_STATUS deassertion | 300 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Tcyc2 | TX_CLK period | 4 | ns | ||
Tdty2 | TX_CLK duty cycle | 50% | |||
Tsu2 | Data setup to TX_CLK rise and TX_CLK fall(1) | 1 | ns | ||
Thd2 | Data hold to TX_CLK rise and TX_CLK fall(1) | 0 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Tcyc3 | PCLK Period | 4 | ns | ||
Tdty3 | PCLK Duty Cycle | 50% | |||
Tdly3 | PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID, RX_STATUS2-0, PHY_STATUS Delay(1)(2) | 1 | 2 | ns |
DESCRIPTION | NOTES | HS | FS | LS | UNIT |
---|---|---|---|---|---|
RX CMD delay | PHY pipeline delays | 2 to 4 | 2 to 4 | 2 to 4 | clocks |
TX start delay | 1 to 2 | 1 to 10 | 1 to 10 | clocks | |
TX end delay | 2 to 5 | clocks | |||
RX start delay | 3 to 8 | clocks | |||
RX end delay | 3 to 8 | 17 to 18 | 122 to 123 | clocks | |
Transmit-Transmit (host only) | Link decision times | 15 to 24 | 7 to 18 | 77 to 247 | clocks |
Receive-Transmit (host or peripheral) | 1 to 14 | 7 to 18 | 77 to 247 | clocks |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Fstart_8bit | Frequency (first transition) ±10% | 54 | 60 | 66 | MHz |
Fsteady | Frequency (steady state) ±500 ppm | 59.97 | 60 | 60.03 | MHz |
Dstart_8bit | Duty cycle (first transition) ±10% | 40% | 50% | 60% | |
Dsteady | Duty cycle (steady state) ±500 ppm | 49.975% | 50% | 50.025% | |
Tsteady | Time to reach steady state frequency and duty cycle after first transition | 1.4 | ms | ||
Tstart_dev | Clock startup time after deassertion of SuspemdM – Peripheral | 5.6 | ms | ||
Tstart_host | Clock startup time after deassertion of SuspemdM – Hold | ms | |||
Tprep | PHY preparation time after first transition of input clock | µs | |||
Tjitter | Jitter | ps | |||
Trise, Tfall | Rise and fall time | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Tsc8, Tsd8 | ULPI_STP set-up time | 6 | ns | ||
Thc8, Thd8 | ULPI_STP hold time | 0 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Tdc9, Tdd9 | ULPI_DIR/ULPI_NXT/ULPI_DATA7-0(1) | 9 | ns |
The USB physical layer handles the low-level USB protocol and signaling, which includes data serialization and deserialization, 8b/10b encoding, analog buffers, elastic buffers, and receiver detection. It shifts the clock domain of the data from the USB rate to one that is compatible with the link-layer controller.
The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXN differential pairs and uses the PIPE to communicate with the link-layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and communicates with the Link-Layer Controller through the ULPI. The reference clock of the TUSB1310A device is connected to an internal crystal oscillator, spread spectrum clock, and with a PLL, which provides clocks to all functional blocks and to the CLKOUT pin for the Link-Layer Controller.
A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan.
The TUSB1310A device has two hardware reset pins, a chip reset RESETN and a logic reset PHY_RESETN. The RESETN is used only at Power On. The PHY_RESETN can be used as a functional reset. The ULPI register also has a software reset.
Until all power sources are supplied, the OUT_ENABLE pin can control the output driver enable. After all power sources are supplied, the chip reset RESETN and a ULPI soft reset is asserted by the Link Layer. The power-up sequence is described in Section 5.3.1.4.
The RESETN sets all internal states to initial values. The Link Layer must hold the PHY in reset through the RESETN until all power sources and the reference clock to the TUSB1310A device are stable. All pins used for strapping options must be set before RESETN deassertion as they are latched by reset deassertion. All strapping option pins have internal pullup or pulldown to set default values, but if any non-default values are desired, they need to be controlled externally by the Link-Layer Controller.
PIPE CONTROL PIN NAME | STATE | VALUE |
---|---|---|
TX_DETRX_LPBK | Inactive | 0 |
TX_ELECIDLE | Active | 1 |
TX_ONESZEROS | Inactive | 0 |
RX_POLARITY | Inactive | 0 |
POWER_DOWN | U2 | 10b |
TX_MARGIN2-0 | Normal operating range | 000b |
TX_DEEMP | –3.5 dB | 1 |
RATE | 5.0 Gbps | 1 |
TX_SWING | Full swing or half swing | 0 or 1 |
RX_TERMINATION | Appropriate state | 0 or 1 |
After power-up, the Link-Layer Controller must set the reset bit in ULPI register. It resets the core but does not reset the ULPI interface or the ULPI registers.
During the ULPI reset, the ULPI_DIR is deasserted. After the reset, the ULPI_DIR is asserted again and the TUSB1310A device sends an RX CMD update to the Link Layer. During the reset, the link must ignore signals on the ULPI_DATA7-0 and must not access the TUSB1310A.
Digital IO buffers use two power supplies, core VDD1P1 and IO VDD1P8. During power up, OUT_ENABLE must be asserted low for proper operation.
Figure 5-1 shows the power-up sequence.
After proper power-supply sequencing, the reference clock on XI starts to operate. On the RESETN deassertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the valid ULPI_CLK and the valid PCLK are driven.
After all stable clocks are provided, the TUSB1310A device allows the Link-Layer Controller to access by deasserting the ULPI_DIR. The Link-Layer Controller sets the Reset bit in the ULPI register. At the PIPE interface, the PHY_STATUS changes from high to low, which indicates that the TUSB1310A device is in the power state specified by the POWER_DOWN signal. After the PHY_STATUS change, the TUSB1310A device is ready for PIPE transactions.
A source clock must be provided through XI or XO from an external crystal or from a square wave clock. The USB 3.0 PLL provides a clock to the PIPE that drives 250 MHz. The USB 2.0 PLL provides a 60-MHz clock to the ULPI.
The CLKOUT is used by the Link-Layer Controller or the MAC in low-power mode. A 120-MHz clock is available on the CLKOUT pin only in the USB U3 power state.
The P1 to P0 transition time is the amount of time for the TUSB1310A device to return to P0 state, after having been in the P1 state. This time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A device asserts PHY_STATUS. The TUSB1310A device asserts PHY_STATUS when it is ready to begin data transmission and reception.
The P2 to P0 transition time is the amount of time for the TUSB1310A device to return to the P0 state, after having been in the P2 state. This time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A device asserts PHY_STATUS. The TUSB1310A device asserts PHY_STATUS when it is ready to begin data transmission and reception.
The P3 to P0 transition time is the amount of time for the TUSB1310A device to go to P0 state, after having been in the P3 state. Time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A device deasserts PHY_STATUS. The TUSB1310A device asserts PHY_STATUS when it is ready to begin data transmission and reception.
The SuperSpeed USB power state transition is controlled by the PIPE POWER_DOWN[1-0] and the Non-SuperSpeed USB power state is transitioned by setting suspendM bit in the ULPI Function control register through the ULPI or by asserting the ULPI_STP.
The USB 3.0 specification improves power consumption by defining four power states, U0, U1, U2, and U3 while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to LTSSM states as described in Table 5-2. For all power state transitions, the Link-Layer Controller must not begin any operational sequences or further power state transitions until the TUSB1310A device has indicated that the internal state transition is completed.
PIPE POWER STATE |
USB POWER STATE | PCLK | PLL | TRANSMITTING | RECEIVING | PHY_STATUS |
---|---|---|---|---|---|---|
P0 | U0, all other LTSSM states | On | On | Active or Idle or LFPS | Active or Idle | One cycle assertion |
P1 | U1 | On | On | Idle or LFPS | Idle | One cycle assertion |
P2 | U2, RxDetect, SS.Inactive | On | On | Idle or LFPS or RxDetect | Idle | One cycle assertion |
P3 | U3, SS.disabled | Off. The PIPE is in an asynchronous mode. | Off | LFPS or RxDetect | Idle | PHY_STATUS is asserted before PCLK is turned off and deasserted when PCLK is fully off. |
When the Link-Layer Controller must transmit LFPS in P1, P2, or P3 state, it must deassert TX_ELECIDLE. The TUSB1310A device generates valid LFPS until the TX_ELECIDLE is asserted. The Link-Layer Controller must assert TX_ELECIDLE before transitioning to P0.
When RX_ELECIDLE is deasserted in P0, P1, P2, or P3, the TUSB1310A device receiver monitors for LFPS except during reset or when RX_TERMINATION is removed for electrical idle.
When the TUSB1310A device is in P0 and is actively transmitting; only RX_POLARITY can be asserted.
POWER STATE | TX_DETRX_LPBK | TX_ELECIDLE | DESCRIPTION |
---|---|---|---|
P0 | 0 | 0 | Transmitting data on TX_DATA |
0 | 1 | Not transmitting and is in electrical idle | |
1 | 0 | Goes into loopback mode | |
1 | 1 | Transmits LFPS signaling | |
P1 | Don’t care | 0 | Transmits LFPS signaling |
1 | Not transmitting and is in electrical idle | ||
P2 | Don’t care | 0 | Transmits LFPS signaling |
0 | 1 | Idle | |
1 | 1 | Does a receiver detection operation | |
P3 | Don’t care | 0 | Transmits LFPS signaling |
1 | Does a receiver detection operation |
The TUSB1310A device has an elastic buffer for clock tolerance compensation, the Link Partner detection, and some received data error detections. The receive data status from SSRXP/SSRXN differential pair presents on RX_STATUS2-0. If an error occurs during a SKP ordered-set (a set of symbols transmitted as a group), the error signaling has precedence. If more than one error occurs on a received byte, the errors have the following priority:
The receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a Link. The elastic buffer must be capable of holding enough symbols to handle worst case differences in frequency and worst case intervals between SKP ordered-sets. A SKP order-set is a set of symbols transmitted as a group. The SKP ordered-sets allows the receiver to adjust the data stream being received prevent the elastic buffer from either overflowing or under-flowing due to any clock tolerance differences.
The TUSB1310A device supports two models, nominal half-full buffer model and nominal empty-buffer mode. For the nominal half-full buffer model, the TUSB1310A device monitors the receive data stream. When a SKP ordered-set is received, the TUSB1310A device adds or removes one SKP order set from each SKP to manage its elastic buffer to keep the buffer as close to half full as possible. Only full SKP ordered sets are added or removed. When a SKP order set is added, the TUSB1310A device asserts an Add SKP code (001b) on the RX_STATUS for one clock cycle. When a SKP order set is removed, the RX_STATUS has a Remove SKP code (010b).
For the nominal empty-buffer model, the TUSB1310A device tries to keep the elasticity buffer as close to empty as possible. When no SKP ordered sets have been received, the TUSB1310A device is required to insert SKP ordered sets into the received data stream.
RX_STATUS2-0 | SKP ADDITION OR REMOVAL | LENGTH |
---|---|---|
001b | 1 SKP Ordered Set added | One clock cycle |
010b | 1 SKP Ordered Set removed |
TX_DETRX_LPBK starts a receiver detection operation to determine if there is a receiver at the other end of the link. When the receiver detect sequence completes, the PHY_STATUS is asserted for one clock and drives the RX_STATUS signals to the appropriate code. When the TX_DETRX_LPBK signal is asserted, the Link-Layer Controller must leave the signal asserted until the PHY_STATUS pulse. When receiver detection is performed in P3, the PHY_STATUS shows the appropriate receiver detect value until the TX_DETRX_LPBK is deasserted.
RX_STATUS2-0 | DETECTED CONDITION | LENGTH |
---|---|---|
000b | Receiver not present | One clock cycle |
011b | Receiver present |
When the TUSB1310A device detects an 8b/10b decode error, it asserts a SUB symbol in the data on the RX_DATA where the bad byte occurred. In the same clock cycle that the SUB symbol is asserted on the RX_DATA, the 8b/10b decode error code (100b) is asserted on the RX_STATUS. An 8b/10b decoding error has priority over all other receiver error codes and could mask out a disparity error occurring on the other byte of data being clocked onto the RX_DATA with the SUB symbol.
RX_STATUS2-0 | DETECTED ERROR | LENGTH |
---|---|---|
100b | 8B/10B Decode Error | Clock cycles during the effected byte is transferred on RX_DATA15-0 |
When the elastic buffer overflows, data is lost during the reception of the data. The elastic buffer overflow error code (101b) is asserted on the RX_STATUS on the PCLK cycle the omitted data would have been asserted. The data asserted on the RX_DATA is still valid data, the elastic buffer overflow error code on the RX_STATUS just marks a discontinuity point in the data stream being received.
When the elastic buffer underflows, SUB symbols are inserted into the data stream on the RX_DATA to fill the holes created by the gaps between valid data. For every PCLK cycle a SUB symbol is asserted on the RX_DATA, an elastic buffer underflow error code (111b) is asserted on the RX_STATUS. In nominal empty-buffer mode, SKP ordered sets are transferred on RX_DATA and the underflow is not signaled.
RX_STATUS2-0 | DETECTED ERROR | LENGTH |
---|---|---|
101b | Elastic Buffer overflow | Clock cycles the omitted data would have appeared |
110b | Elastic Buffer underflow | Clock cycles during the SUB symbol presence on RX_DATA15-0 |
When the TUSB1310A device detects a disparity error, it asserts a disparity error code (111b) on the RX_STATUS in the same PCLK cycle it asserts the erroneous data on the RX_DATA. The disparity code does not discern which byte on the RX_DATA is the erroneous data.
RX_STATUS2-0 | DETECTED ERROR | LENGTH |
---|---|---|
111b | Disparity Error | Clock cycles during the effected byte is transferred on RX_DATA15-0 |
The TUSB1310A device begins an internal-loopback operation from SSRXP/SSRXN differential pairs to SSTXP/SSTXN differential pairs when the TX_DETRX_LPBK is asserted while holding TX_ELECIDLE deasserted. The TUSB1310A device stops transmitting data to the SSTXP/SSTXN signaling pair from the TX_DATA and begins transmitting on the SSTXP/SSTXN signaling pair the data received at the SSRXP/SSRXN signaling pair. This data is not routed through the 8b/10b coding/encoding paths. While in the loopback operation, the received data is still sent to the RX_DATA. The data sent to the RX_DATA is routed through the 10b/8b decoder.
The TX_DETRX_LPBK deassertion terminates the loopback operation and returns to transmitting TX_DATA over the SSTXP/SSTXN signaling pair. The TUSB1310A device only transitions out of loopback on detection of LFPS signaling by transitioning to P2 state and starting the LFPS handshake.
The adaptive equalizer dynamically adjusts the forward gain and peaking of the analog equalizer to minimize the jitter at the cross over point of the eye diagram, which allows for greater jitter tolerance in the RX.
USB 3.0 is a physical SuperSpeed bus combined in parallel with a physical USB 2.0, according to the USB 3.0 Specification. Each PHY operates independently on a separate data bus. Following this specification, the USB architecture of the TUSB1310A device achieves different working modes. Simultaneous operation of USB 3.0 and USB 2.0 modes is not allowed for peripheral devices.
At an electrical level, each SuperSpeed differential link is initialized by enabling its receiver termination. The transmitter is responsible for detecting the far end receiver termination as an indication of a bus connection and informing the link layer so the connect status can be factored into link operation and management. The SuperSpeed link is disabled, for example, when the low impedance receiver termination of a port is removed.
When the TUSB1310A is connected to an electrical environment that only supports high-speed, full-speed, or low-speed connections, the SuperSpeed USB 3.0 connectivity is disabled. In this case, the USB 2.0 capabilities are compliant with the USB 2.0 specification.
The TUSB1310A device supports synchronous mode and low-power mode. The default mode is synchronous mode.
The synchronous mode is a normal operation mode. The ULPI_DATA are synchronous to ULPI_CLK. The low-power mode is used during power down and no ULPI_CLK. The TUSB1310A device sets ULPI_DIR to output and drives LineState signals and interrupts.
SYNCHRONOUS | LOW POWER |
---|---|
ULPI_CLK(OUT) | |
ULPI_DATA7(I/O) | |
ULPI_DATA6(I/O) | |
ULPI_DATA5(I/O) | |
ULPI_DATA4(I/O) | |
ULPI_DATA3(I/O) | ULPI_INT (OUT) |
ULPI_DATA2(I/O) | |
ULPI_DATA1(I/O) | ULPI_LINESTATE1(OUT) |
ULPI_DATA0(I/O) | ULPI_LINE_STATE0 (OUT) |
ULPI_DIR(OUT) | |
ULPI_STP(IN) | |
ULPI_NXT(OUT) |
ACCESS CODE | EXPANDED NAME | DESCRIPTION |
---|---|---|
Rd | Read | Register can be read. Read-only if this is the only mode given. |
Wr | Write | Pattern on the data bus is written over all bits of the register. |
S | Set | Pattern on the data bus is OR'd with and written into the register. |
C | Clear | Pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit is set to zero (cleared). |
The TUSB1310A device contains the ULPI registers consisting of an immediate register set and an extended register set.
REGISTER NAME | ADDRESS (6 BITS) | |||
---|---|---|---|---|
Rd | Wr | Set | Clr | |
IMMEDIATE REGISTER SET | ||||
Vendor ID Low | 00h | |||
Vendor ID High | 01h | |||
Product ID Low | 02h | |||
Product ID High | 03h | |||
Function Control | 04h–06h | 04h | 05h | 06h |
Interface Control | 07h–09h | 07h | 08h | 09h |
OTG Control | 0Ah–0Ch | 0Ah | 0Bh | 0Ch |
USB Interrupt Enable Rising | 0Dh–0Fh | 0Dh | 0Eh | 0Fh |
USB Interrupt Enable Falling | 10h–12h | 10h | 11h | 12h |
USB Interrupt Status | 13h | 13h | ||
USB Interrupt Latch | 14h | 14h | ||
Debug | 15h | |||
Scratch Register | 16h–18h | 16h | 17h | 18h |
Reserved | 19h–2Eh |
ADDRESS | BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|---|
00h | 7:00 | Vendor ID Low | Rd | 51h | Lower byte of vendor ID supplied by USB-IF |
01h | 7:00 | Vendor ID High | Rd | 04h | Upper byte of vendor ID supplied by USB-IF |
02h | 7:00 | Product ID Low | Rd | 10h | Lower byte of vendor ID supplied by vendor |
03h | 7:00 | Product ID High | Rd | 13h | Upper byte of vendor ID supplied by vendor |
Address: 04h-06h (Read), 04h (Write), 05h (Set), 06h (Clear)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
1:0 | XcvrSelect | Rd, Wr, S, C | 1h | Selects the required transceiver speed 00b : Enable HS transceiver 01b: Enable FS transceiver 10b: Enable LS transceiver 11b: Enable FS transceiver for LS packets (FS preamble is automatically prepended) |
2 | TermSelect | Rd, Wr, S, C | 0 | Controls the internal 1.5-kΩ pullup resister and 45-Ω HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. Because low speed peripherals never support full speed or hi-speed, providing the 1.5 kΩ on DM for low speed is optional. |
4:3 | OpMode | Rd, Wr, S, C | 00 | Selects the required bit encoding style during transmit 00 : Normal operation 01: Nondriving 10: Disable bit-stuff and NRZI encoding 11: Do not automatically add SYNC and EOP when transmitting. Must be used only for HS packets. |
5 | Reset | Rd, Wr, S, C | 0 | Active High transceiver reset. After the Link sets this bit, the TUSB1310A device must assert the ULPI_DIR and reset the ULPI. When the reset is completed, the PHY deasserts the ULPI_DIR and automatically clears this bit. After deasserting the ULPI_DIR, the PHY must re-assert the ULPI_DIR and send an RX CMD update on the Link-Layer Controller. The Link-Layer Controller must wait for the ULPI_DIR to deassert before using the ULPI bus. Does not reset the ULPI or ULPI register set. |
6 | SuspendM | Rd, Wr, S, C | 1h | Active low PHY suspend. Put the TUSB1310A device into low-power mode. The PHY can power down all blocks except the full speed receiver, OTG com-parators, and the ULPI pins. The PHY must automatically set this bit to 1 when low-power mode is exited. 0: Low-power mode 1: Powered |
7 | Reserved | Rd | 0 | Reserved |
Address: 07-09h (Read), 07h (Write), 08h (Set), 09h (Clear)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | Reserved | Rd | 0b | Reserved, only write a 0 to this bit |
1 | Reserved | Rd | 0b | Reserved, only write a 0 to this bit |
2 | Reserved | Rd | 0h | Reserved |
3 | ClockSuspendM | Rd, Wr, S, C | 0b | Active low clock suspend. Valid only in serial mode. Powers down the internal clock circuitry only. Valid only when SuspendM = 1. The TUSB1310A device must ignore ClockSuspend when SuspendM = 0. By default, the clock is not be powered in serial mode. 0 : Clock is not powered in serial mode 1 : Clock is powered in serial mode |
6:4 | Reserved | Rd | 0h | Reserved |
7 | Interface Protect Disable |
Rd, Wr, S, C | 0 | Controls internal pull-ups and pull-downs on both the ULPI_STP and the ULPI_DATA for protecting the ULPI when the Link-Layer Controller puts the signals to tri-state value. 0 Enables the pullup and pulldown 1 Disables the pullup and pulldown |
Address: 0Ah-0Ch (Read), 0Ah (Write), 0Bh (Set), 0Ch (Clear). Controls UTMI+ OTG functions of the PHY.
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | Reserved | Rd | 0b | This bit is not implemented and returns a 0b when read |
1 | DpPulldown | Rd, Wr, S, C | 1b | Enables the 15-kΩ pulldown resistor on D+ 0 Pulldown resistor not connected to D+ 1 Pulldown resistor connected to D+ |
2 | DmPulldown | Rd, Wr, S, C | 1h | Enables the 15-kΩ pulldown resistor on D– 0 Pulldown resistor not connected to D– 1 Pulldown resistor connected to D– |
7:3 | Reserved | Rd | 0h | These bits are not implemented and return zeros when read |
Address: 0D-0Fh (Read), 0Dh (Write), 0Eh (Set), 0Fh (Clear)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | Hostdisconnect Rise | Rd, Wr, S, C | 1b | Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). |
Address: 10-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | Hostdisconnect Fall | Rd, Wr, S, C | 1b | Generate an interrupt event notification when Host-disconnect changes from high to low. Applicable only in host. |
Address: 13h (Read-only)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | Hostdisconnect Fall | Rd, Wr, S, C | 1b | Generate an interrupt event notification when Host-disconnect changes from high to low. Applicable only in host. |
Address: 14h (Read-only with auto-clear)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | Hostdisconnect Fall | Rd, Wr, S, C | 1b | Set to 1b by the PHY when an unmasked event occurs on Host-disconnect. Cleared when this register is read. Applicable only in host mode. |
Address: 15h (Read-only)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
0 | LineState0 | Rd | 0 | Contains the current value of LineState0 |
1 | LineState1 | Rd | 0 | Contains the current value of LineState1 |
7:2 | Reserved | Rd | 0 | Reserved |
Address: 16-18h (Read), 16h (Write), 17h (Set), 18h (Clear)
BITS | NAME | ACCESS | RESET | DESCRIPTION |
---|---|---|---|---|
7:0 | Scratch | Rd, Wr, S, C | 00 | Empty register byte for testing purposes. Software can read, write, set, and clear this register and the TUSB1310A device functionality is not be affected. |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Texas Instruments’ TUSB1310A device is a single port, 5.0-Gbps USB 3.0 physical layer transceiver that is available in a lead-free, 175-ball, 12-mm × 12-mm NFBGA package (ZAY). The link controller interfaces to the TUSB1310A device are through a PIPE (16-bit wide operating at 250 MHz) and a ULPI (8-bit wide operating at 60 MHz) interface. The USB connector interfaces to the TUSB1310A device through a USB 3.0 SuperSpeed USB differential pair (TX and RX) and USB 2.0 differential pair (DP/DM).
Figure 6-1 represents a typical implementation of the TUSB1310A USB 3.0 physical layer transceiver that operates off of a single crystal or an external reference clock. The reference frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A device provides a clock to the USB link layer controllers. The single reference clock allows the TUSB1310A device to provide a cost effective USB 3.0 solution with few external components and a minimum implementation cost.
Reference clock jitter is an important parameter. Jitter on the reference clock degrades both the transmit eye and receiver jitter tolerance, no matter how clean the rest of the PLL is, thereby impairing system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock detection mechanism, forcing the lock detector to issue an unlock signal. A good quality, low jitter reference clock is required to achieve compliance with supported USB 3.0 standards. For example, USB 3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function [JTF]). As the PLL typically has a number of additional jitter components, the reference clock jitter must be considerably below the overall jitter budget.
If an external clock source is used, XI must be tied to the clock source and XO must be left floating.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency tolerance | Operational temperature | ±50 | ppm | ||
Frequency stability | 1 year aging | ±50 | ppm | ||
Rise and Fall time | 20% to 80% | 6 | nsec | ||
Reference clock RJ with JTF (1 sigma)(1)(2) | 0.8 | psec | |||
Reference clock TJ with JTF (total p-p)(2)(3) | 25 | psec | |||
Reference clock jitter (absolute p-p)(4) | 50 | psec |
Either a 20-MHz, 25-MHz, 30-MHz, or 40-MHz crystal can be selected. A parallel, 20-pF load crystal must be used if a crystal source is used.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency tolerance | Operational temperature | ±50 | ppm | ||
Frequency stability | 1 year aging | ±50 | ppm | ||
Load capacitance | 12 | 20 | 24 | pF |
Components must be placed close to the TUSB1310A device to reduce the trace length of the interface between the components and the TUSB1310A. If external capacitors cannot accommodate a close placement, shielding to ground is recommended.
The following rules apply for differential pair signals (DP/DM, SSTXP/SSTXN, and SSRXP/SSRXN):
Figure 6-3 and Figure 6-4 are for visual reference only.
The TUSB1310A device supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection must adhere to the following guidelines.
Because XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. It is also recommended to minimize the capacitance between XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC must not be connected to PCB ground.
Load capacitance (CLOAD) of the crystal varying with the crystal vendors is the total capacitance value of the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2 in Figure 6-5. The trace length between the decoupling capacitors and the corresponding power pins on the TUSB1310A device must be minimized. It is also recommended that the trace length from the capacitor pad to the power or ground plane be minimized.
The TUSB1310A requires 1.1-V and 1.8-V digital power sources. Both VDD1P1 and VDD1P8 supplies must have 0.1-μF bypass capacitors to VSS (ground) in order for proper operation. The recommendation is one capacitor for each power terminal. Place the capacitor as close as possible to the terminal on the device and keep trace length to a minimum. Smaller value capacitors like 0.01-μF are also recommended on the digital supply terminals. When placing and connecting all bypass capacitors, high-speed board design rules must be followed.
Because circuit noise on the analog power terminals must be minimized, a Pi-type filter is recommended for each supply. Analog power terminals must have a 0.1-μF bypass capacitor connected to VSSA (ground) for proper operation. Place the capacitor as close as possible to the terminal on the device and keep trace length to a minimum. Smaller value capacitors (0.01-μF) are also recommended on the analog supply terminals.
When selecting bypass capacitors for the TUSB1310A device, X7R-type capacitors are recommended. The frequency versus impedance curves, quality, stability, and cost of these capacitors make them a logical choice for most computer systems.
The selection of bulk capacitors with low-ESR specifications is recommended to minimize low frequency power supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolytic capacitors. These capacitors typically have ESR specifications that are less than 0.01 Ω at 100 kHz. Also, several manufacturers sell D-size surface mount specialty polymer solid aluminum electrolytic capacitors with ESR specifications slightly higher than 0.01 Ω at 100 kHz. Both of these bulk capacitor options significantly reduce low frequency power supply noise and ripple.
The following documents describe the TUSB1310A transceiver. Copies of these documents are available on the Internet at www.ti.com.
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.