5.3.1.1 RESETN and PHY_RESETN: Hardware Reset

The RESETN sets all internal states to initial values. The Link Layer must hold the PHY in reset through the RESETN until all power sources and the reference clock to the TUSB1310A device are stable. All pins used for strapping options must be set before RESETN deassertion as they are latched by reset deassertion. All strapping option pins have internal pullup or pulldown to set default values, but if any non-default values are desired, they need to be controlled externally by the Link-Layer Controller.

5.3.1.2 ULPI Reset: Software Reset

After power-up, the Link-Layer Controller must set the reset bit in ULPI register. It resets the core but does not reset the ULPI interface or the ULPI registers.

During the ULPI reset, the ULPI_DIR is deasserted. After the reset, the ULPI_DIR is asserted again and the TUSB1310A device sends an RX CMD update to the Link Layer. During the reset, the link must ignore signals on the ULPI_DATA7-0 and must not access the TUSB1310A.

5.3.1.3 OUT_ENABLE: Output Enable

Digital IO buffers use two power supplies, core VDD1P1 and IO VDD1P8. During power up, OUT_ENABLE must be asserted low for proper operation.

5.3.1.4 Power-Up Sequence

Figure 5-1 shows the power-up sequence.

Figure 5-1 Power-Up Sequence

After proper power-supply sequencing, the reference clock on XI starts to operate. On the RESETN deassertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the valid ULPI_CLK and the valid PCLK are driven.

After all stable clocks are provided, the TUSB1310A device allows the Link-Layer Controller to access by deasserting the ULPI_DIR. The Link-Layer Controller sets the Reset bit in the ULPI register. At the PIPE interface, the PHY_STATUS changes from high to low, which indicates that the TUSB1310A device is in the power state specified by the POWER_DOWN signal. After the PHY_STATUS change, the TUSB1310A device is ready for PIPE transactions.

5.3.2.1 Clock Distribution

A source clock must be provided through XI or XO from an external crystal or from a square wave clock. The USB 3.0 PLL provides a clock to the PIPE that drives 250 MHz. The USB 2.0 PLL provides a 60-MHz clock to the ULPI.

5.3.2.2 Output Clock

The CLKOUT is used by the Link-Layer Controller or the MAC in low-power mode. A 120-MHz clock is available on the CLKOUT pin only in the USB U3 power state.

5.3.4.1 USB Power Management

The USB 3.0 specification improves power consumption by defining four power states, U0, U1, U2, and U3 while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to LTSSM states as described in Table 5-2. For all power state transitions, the Link-Layer Controller must not begin any operational sequences or further power state transitions until the TUSB1310A device has indicated that the internal state transition is completed.

When the Link-Layer Controller must transmit LFPS in P1, P2, or P3 state, it must deassert TX_ELECIDLE. The TUSB1310A device generates valid LFPS until the TX_ELECIDLE is asserted. The Link-Layer Controller must assert TX_ELECIDLE before transitioning to P0.

When RX_ELECIDLE is deasserted in P0, P1, P2, or P3, the TUSB1310A device receiver monitors for LFPS except during reset or when RX_TERMINATION is removed for electrical idle.

When the TUSB1310A device is in P0 and is actively transmitting; only RX_POLARITY can be asserted.

5.3.5.1 Clock Tolerance Compensation

The receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a Link. The elastic buffer must be capable of holding enough symbols to handle worst case differences in frequency and worst case intervals between SKP ordered-sets. A SKP order-set is a set of symbols transmitted as a group. The SKP ordered-sets allows the receiver to adjust the data stream being received prevent the elastic buffer from either overflowing or under-flowing due to any clock tolerance differences.

The TUSB1310A device supports two models, nominal half-full buffer model and nominal empty-buffer mode. For the nominal half-full buffer model, the TUSB1310A device monitors the receive data stream. When a SKP ordered-set is received, the TUSB1310A device adds or removes one SKP order set from each SKP to manage its elastic buffer to keep the buffer as close to half full as possible. Only full SKP ordered sets are added or removed. When a SKP order set is added, the TUSB1310A device asserts an Add SKP code (001b) on the RX_STATUS for one clock cycle. When a SKP order set is removed, the RX_STATUS has a Remove SKP code (010b).

For the nominal empty-buffer model, the TUSB1310A device tries to keep the elasticity buffer as close to empty as possible. When no SKP ordered sets have been received, the TUSB1310A device is required to insert SKP ordered sets into the received data stream.

5.3.5.2 Receiver Detection

TX_DETRX_LPBK starts a receiver detection operation to determine if there is a receiver at the other end of the link. When the receiver detect sequence completes, the PHY_STATUS is asserted for one clock and drives the RX_STATUS signals to the appropriate code. When the TX_DETRX_LPBK signal is asserted, the Link-Layer Controller must leave the signal asserted until the PHY_STATUS pulse. When receiver detection is performed in P3, the PHY_STATUS shows the appropriate receiver detect value until the TX_DETRX_LPBK is deasserted.

5.3.5.3 8b/10b Decode Errors

When the TUSB1310A device detects an 8b/10b decode error, it asserts a SUB symbol in the data on the RX_DATA where the bad byte occurred. In the same clock cycle that the SUB symbol is asserted on the RX_DATA, the 8b/10b decode error code (100b) is asserted on the RX_STATUS. An 8b/10b decoding error has priority over all other receiver error codes and could mask out a disparity error occurring on the other byte of data being clocked onto the RX_DATA with the SUB symbol.

5.3.5.4 Elastic Buffer Errors

When the elastic buffer overflows, data is lost during the reception of the data. The elastic buffer overflow error code (101b) is asserted on the RX_STATUS on the PCLK cycle the omitted data would have been asserted. The data asserted on the RX_DATA is still valid data, the elastic buffer overflow error code on the RX_STATUS just marks a discontinuity point in the data stream being received.

When the elastic buffer underflows, SUB symbols are inserted into the data stream on the RX_DATA to fill the holes created by the gaps between valid data. For every PCLK cycle a SUB symbol is asserted on the RX_DATA, an elastic buffer underflow error code (111b) is asserted on the RX_STATUS. In nominal empty-buffer mode, SKP ordered sets are transferred on RX_DATA and the underflow is not signaled.

5.3.5.5 Disparity Errors

When the TUSB1310A device detects a disparity error, it asserts a disparity error code (111b) on the RX_STATUS in the same PCLK cycle it asserts the erroneous data on the RX_DATA. The disparity code does not discern which byte on the RX_DATA is the erroneous data.

Table 5-9 ULPI Synchronous and Low-Power Mode Functions

Table 5-12 Vendor ID and Product ID

Table 5-13 Function Control

Table 5-14 Interface Control

Table 5-15 OTG Control Register

Table 5-16 USB Interrupt Enable Rising

Table 5-17 USB Interrupt Enable Falling

Table 5-18 USB Interrupt Status

Table 5-19 USB Interrupt Latch

Table 5-20 Debug

Table 5-21 Scratch Register