SLLS372I March   2000  – March 2017 TUSB2036

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Differential Driver Switching Characteristics (Full Speed Mode)
    7. 7.7 Differential Driver Switching Characteristics (Low Speed Mode)
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB Power Management
      2. 8.3.2 Clock Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 2-3 Programmable Downstream Ports
      2. 8.4.2 Vendor ID and Product ID With External Serial EEPROM
    5. 8.5 Programming
      1. 8.5.1 Programming the EEPROM
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 TUSB2036 Power Supply
    2. 10.2 Downstream Port Power
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

VF Package
32-PIN HLQFP
(Top View)
TUSB2036 vf_po_lls372.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BUSPWR 8 I Power source indicator. BUSPWR is an active-low input that indicates whether the downstream ports source their power from the USB cable or a local power supply. For the bus-power mode, this pin must be pulled low, and for the self-powered mode, this pin must be pulled to 3.3 V. Input must not change dynamically during operation.
DM0 2 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1 11 I/O USB differential data minus. DM1–DM3 paired with DP1–DP3 support up to four downstream USB ports.
DM2 15
DM3 19
DP0 1 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
DP0PUR 27 O Pullup resistor connection. When a system reset happens (RESET being driven to low, but not USB reset) or any logic level change on BUSPWR pin, DP0PUR output is inactive (floating) until the internal counter reaches a 15-ms time period. After the counter expires, DP0PUR is driven to the VCC (3.3 V) level thereafter until the next system reset event occurs or there is a BUSPWR logic level change.
DP1 12 I/O USB differential data plus. DP1–DP3 paired with DM1–DM3 support up to four downstream USB ports.
DP2 16
DP3 20
EECLK 5 O EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK pin is disabled and must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output to the EEPROM with a 100-μA internal pulldown.
EEDATA/ GANGED 6 I/O EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED selects between ganged or per-port power overcurrent detection for the downstream ports. When EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100-μA pulldown. This standard TTL input must not change dynamically during operation.
EXTMEM 26 I When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is low, pins 5 and 6 are configured as the clock and data pins of the serial EEPROM interface, respectively.
GND 7, 28 GND pins must be tied to ground for proper operation.
OCPROT/ PWRSW 21 I Overcurrent Protection for bus-powered hub (active low). /Power Switching for self-powered hub (active low). The pin has a different meaning for the bus or self-powered hub. If the pin is logic high the internal pulldown is disabled.(1) (2)
OVRCUR1 10 I Overcurrent input. OVRCUR1 − OVRCUR3 are active low. For per-port overcurrent detection, one overcurrent input is available for each of the three downstream ports. In the ganged mode, any OVRCUR input may be used and all OVRCUR pins must be tied together. OVRCUR pins are active low inputs with noise filtering logic. Each OVRCURn input is sampled every 2 ms and any input which is valid for two consecutive samples will be passed to the internal logic. OVRCUR3 has an internal pull-up that can be enabled for the 2-port operation.
OVRCUR2 14
OVRCUR3 18
PWRON1 9 O Power-on/-off control signals. PWRON1–PWRON3 are active low, push-pull outputs that enables the external power switch device. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these pins must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals.
PWRON2 13
PWRON3 17
RESET 4 I RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window.
SUSPND 32 O Suspend status. SUSPND is an active high output available for external logic power-down operations. During the suspend mode, SUSPND is high. SUSPND is low for normal operation.
MODE 31 I Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal core of the device and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be used.
NP3 24 I Number of ports is 3. Active low input. A logic 0 configures the system to use 3 ports. A logic 1 configures the system to use 2 ports.
NPINT0 22 I Number of ports internal to hub system, which are permanently attached (see Table 1).
NPINT1 23
VCC 3, 25 I 3.3-V supply voltage
XTAL1/CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed.
XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This pin must be left open when using an oscillator.
(1) If the hub is implemented to be bus-powered (via BUSPWR tying to GND):
  • TUSB2036 reports to the host that the hub end-product downstream ports are power-switched (this is required by the USB 2.0 specification). Hub end-product vendor has to ensure the actual end-product implementation meets this specification requirement.
  • Pin 21 acts as overcurrent protection (OCPROT) implementation indication pin for the bus-powered hub. The overcurrent protection implementation is reported through the wHubCharacteristics. D4 bit in the hub descriptor.
  • When OCPROT is low, the TUSB2036 reports to the host that the hub end-product provides overcurrent protection and the wHubCharacteristics. D4 bit is set to 0.
  • When OCPROT is high, the TUSB2036 reports to the host that the hub end-product does not provide overcurrent protection and the wHubCharacteristics. D4 bit is set to 1.
(2) If the hub is implemented to be self-powered (via BUSPWR tying to 3.3-V VCC):
  • TUSB2036 reports to the host that the hub end-product provides overcurrent protection to the downstream ports (this is required by the USB 2.0 specification). Hub end-product vendor has to ensure the actual end-product implementation meets this specification requirement.
  • Pin 21 acts as power switching (PWRSW) implementation indication pin for the self-powered hub. The power-switching implementation is reported through the bPwrOn2PwrGood field in the hub descriptor.
  • When PWRSW is low, the TUSB2036 reports to the host that the hub end-product has port power switching at the downstream ports and the bPwrOn2PwrGood is set to 50 units (100 ms).
  • When PWRSW is high, the TUSB2036 reports to the host that the hub end-product does not have port power switching at the downstream ports and the bPwrOn2PwrGood is set to 0 units (0 ms).