SLLSF36A August   2017  – September 2017 TUSB214-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EQ
      2. 7.3.2 DC BOOST
      3. 7.3.3 BC1.2 CDP Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Speed (LS) Mode
      2. 7.4.2 Full Speed (FS) Mode
      3. 7.4.3 High Speed (HS) Mode
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 I2C Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The primary purpose of the TUSB214-Q1 is to re-store the signal integrity of a USB High Speed channel up to the USB receptacle. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace and other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye mask. Proper use of the TUSB214-Q1 can help to pass this eye mask.

A secondary purpose is to use the CD pin of the TUSB214-Q1 to control other blocks on the customer platform if so desired. Also, TUSB214-Q1 can be used as a CDP controller.

8.2 Typical Application

A typical application is shown in Figure 6. In this setup, D2P and D2M face the USB connector while D1P and D1M face the USB host. If desired, the orientation may be reversed [that is, D2 faces transceiver and D1 faces connector].

TUSB214-Q1 SLLSEX5_Typ_App.gif Figure 6. Typical Application

8.2.1 Design Requirements

For this design example, use parameters shown in the table below.

Table 3. Design Parameters

PARAMETER VALUE
VCC (3.0V to 3.6V) 3.3 V
I2C support required in system (Yes/No) No
AC Boost REQ Level AC Boost Level 2:
REQ = 3.83 K
0 Ω 0
1.69 k ±1% 1
3.83 k ±1% 2
DNI 3
DC Boost RDC1 RDC2 Level Mid DC Level:
RDC1 = DNI
RDC2 = DNI
22 kΩ - 47 kΩ Do Not Install (DNI) 40 mV Low DC Boost
DNI DNI 60 mV Mid DC Boost
DNI 22 kΩ - 47 kΩ 80 mV High DC Boost

8.2.2 Detailed Design Procedure

TUSB214-Q1 requires a valid reset signal as described in the power supply recommendations section. The capacitor at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.

VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.

The ideal AC/DC Boost setting is dependent upon the signal chain loss characteristics of the target platform. The general recommendation is to start with AC Boost level 0, and then increment to AC Boost level 1, etc. when needed. Same applies to the DC boost setting where it is recommended to plan for the required pad to change boost settings.

In order for the TUSB214-Q1 to recognize any change to the AC or DC boost settings, the RSTN pin must be toggled. This is because the EQ and DC_BOOST pins are latched on power up and the pins are ignored thereafter.

Further D1P has to be shorted to D2P and D1M shorted to D2M on the board for correct functionality of the device.

Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.

Table 4. Platform Placement Guideline

PLATFORM GOAL SUGGESTED TUSB214-Q1 PLACEMENT
Pass USB Near End Mask Close to measurement point
Pass USB Far End Eye Mask Close to USB PHY
Cascade multiple TUSB214-Q1 to improve device enumeration Midway between each USB interconnect
TUSB214-Q1 SLLSEX5_Schematic.gif
D2P must be shorted to D1P on PCB.
D2N must be shorted to D1N on PCB.
Figure 7. Reference Schematic

8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram

NOTE

USB-IF certification tests for High Speed eye masks require the mandated use of the USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope probes. Instead they use SMA cables. More information can be found at the USB-IF Compliance Updates Page. It is located under the ‘Electricals’ section, ID 86 dated March 2013.

The following procedure must be followed before using any oscilloscope compliance software to construct a USB High Speed Eye Mask:

8.2.2.1.1 For a Host Side Application

  1. Configure the TUSB214-Q1 to the desired AC and DC boost settings.
  2. Power on (or toggle the RSTN pin if already powered on) the TUSB214-Q1
  3. Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB214-Q1
  4. Enable the host to transmit USB TEST_PACKET
  5. Execute the oscilloscope USB compliance software.
  6. Repeat the above steps in order to re-test TUSB214-Q1 with different AC and DC boost settings.

8.2.2.1.2 For a Device Side Application

  1. Configure the TUSB214-Q1 to the desired AC and DC boost settings.
  2. Power on (or toggle the RSTN pin if already powered on) the TUSB214-Q1
  3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB214-Q1. Ensure that the USB-IF device test fixture is configured to the ‘INIT’ position
  4. Allow the host to enumerate the device
  5. Enable the device to transmit USB TEST_PACKET
  6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the device-side test fixture is configured to the ‘TEST’ position.
  7. Execute the oscilloscope USB compliance software.
  8. Repeat the above steps in order to re-test TUSB214-Q1 with different AC and DC boost settings.

8.2.3 Application Curves

TUSB214-Q1 bench_setup.gif Figure 8. Eye Diagram Bench Setup
TUSB214-Q1 SLLSEX5_scope_1.gif Figure 9. No TUSB214-Q1
TUSB214-Q1 SLLSEX5_scope_2.gif Figure 10. Low DC Boost, AC Boost Level 0
TUSB214-Q1 SLLSEX5_scope_4.gif Figure 12. High DC Boost, AC Boost Level 0
TUSB214-Q1 SLLSEX5_scope_6.gif Figure 14. Mid DC Boost, AC Boost Level 1
TUSB214-Q1 SLLSEX5_scope_8.gif Figure 16. Low DC Boost, AC Boost Level 2
TUSB214-Q1 SLLSEX5_scope_10.gif Figure 18. High DC Boost, AC Boost Level 2
TUSB214-Q1 SLLSEX5_scope_12.gif Figure 20. Mid DC Boost, AC Boost Level 3
TUSB214-Q1 SLLSEX5_scope_3.gif Figure 11. Mid DC Boost, AC Boost Level 0
TUSB214-Q1 SLLSEX5_scope_5.gif Figure 13. Low DC Boost, AC Boost Level 1
TUSB214-Q1 SLLSEX5_scope_7.gif Figure 15. High DC Boost, AC Boost Level 1
TUSB214-Q1 SLLSEX5_scope_9.gif Figure 17. Mid DC Boost, AC Boost Level 2
TUSB214-Q1 SLLSEX5_scope_11.gif Figure 19. Low DC Boost, AC Boost Level 3
TUSB214-Q1 SLLSEX5_scope_13.gif Figure 21. High DC Boost, AC Boost Level 3