7.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]
CONFIGURATION is shown in Figure 4 and described in Table 5.
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This register is selecting device mode.
Figure 4. CONFIGURATION Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
CFG_ACTIVE |
RH/W-X |
RH/W-0x1 |
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Table 5. CONFIGURATION Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-1 |
RESERVED |
RH/W |
X |
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values
|
0 |
CFG_ACTIVE |
RH/W |
0x1 |
Configuration mode
After reset, if I2C mode is true (SCL and SDA are both pulled high) set the bit to get into configuration mode and clear to return to normal mode.
0x0 = NORMAL MODE
0x1 = CONFIGURATION MODE
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