SLLSFK6 September   2021 TUSB217A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High-Speed Boost
      2. 8.3.2 RX Sensitivity
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Speed (LS) Mode
      2. 8.4.2 Full-Speed (FS) Mode
      3. 8.4.3 High-Speed (HS) Mode
      4. 8.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 8.4.5 Shutdown Mode
      6. 8.4.6 I2C Mode
      7. 8.4.7 BC 1.2 Battery Charging Controller
    5. 8.5 TUSB217A-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 9.2.2.1.1 For a Host Side Application
          2. 9.2.2.1.2 For a Device Side Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.3 High-Speed (HS) Mode

TUSB217A-Q1 automatically detects a HS connection and will enable signal compensation as determined by the configuration of the RX_SEN pin and the external pull down resistance on its BOOST pin.

CD pin and ENA_HS pin are asserted high when high-speed boost is active.