I²C target interface enables access to internal registers by the system application processor. The primary function of the interface is to enable configuring various PHY parameters, controlling the GPIO pins, and enabling USB-BC functions. The TUSB2E11 repeater functions operate upon power up without requiring I²C configuration.

The TUSB2E11 has I²C 7-bit target address of 0x3E. 8-bit address of Write: 0x7C and Read: 0x7D.

I²C default target address can be changed at the factory through one time programming.

I²C drive strength can be changed through the I²C.

Figure 8-5 I²C Write with Data

Use the following procedure to write data to the TUSB2E11 I²C registers (refer to Figure 8-5):

1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB2E11 acknowledges the address cycle.
3. The host presents the register offset within the TUSB2E11 to be written, consisting of one byte of data, MSB-first.
4. The TUSB2E11 acknowledges the sub-address cycle.
5. The host presents the first byte of data to be written to the I²C register.
6. The TUSB2E11 acknowledges the byte transfer.
7. The host may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB2E11.
8. The host terminates the write operation by generating a stop condition (P).

Figure 8-6 I²C Read Without Repeated Start

Use the following procedure to write data to the TUSB2E11 I²C registers without a repeated Start (refer Figure 8-6).

1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
2. The TUSB2E11 acknowledges the 7-bit address cycle.
3. Following the acknowledge the host continues sending clock.
4. The TUSB2E11 transmit the contents of the memory registers MSB-first starting at register 00h or last read register offset+1. If a write to the I²C register occurred prior to the read, then the TUSB2E11 shall start at the register offset specified in the write.
5. The TUSB2E11 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each byte transfer; the I²C host acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB2E11 transmits the next byte of data as long as host provides the clock. If a NAK is received, the TUSB2E11 stops providing data and waits for a stop condition (P).
7. The host terminates the write operation by generating a stop condition (P).

Figure 8-7 I²C Read with Repeated Start

Use the following procedure to write data to the TUSB2E11 I²C registers with a repeated Start (refer Figure 8-7).

1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB2E11 acknowledges the 7-bit address cycle.
3. The host presents the register offset within the TUSB2E11 to be written, consisting of one byte of data, MSB-first.
4. The TUSB2E11 acknowledges the register offset cycle.
5. The host presents a repeated start condition (Sr).
6. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a one-value “W/R” bit to indicate a read cycle.
7. The TUSB2E11 acknowledges the 7-bit address cycle.
8. The TUSB2E11 transmit the contents of the memory registers MSB-first starting at the register offset.
9. The TUSB2E11 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each byte transfer; the I²C host acknowledges reception of each data byte transfer.
10. If an ACK is received, the TUSB2E11 transmits the next byte of data as long as host provides the clock. If a NAK is received, the TUSB2E11 stops providing data and waits for a stop condition (P).
11. The host terminates the read operation by generating a stop condition (P).

Figure 8-8 I²C Write Without Data

Use the following procedure to set a starting sub-address for I²C reads (refer to Figure 8-8).

1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E11 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB2E11 acknowledges the address cycle.
3. The host presents the register offset within the TUSB2E11 to be written, consisting of one byte of data, MSB-first.
4. The TUSB2E11 acknowledges the register offset cycle.
5. The host terminates the write operation by generating a stop condition (P).

Figure 8-9 I²C Timing Diagram