SLLSFI4D November 2021 – April 2024 TUSB2E11
PRODUCTION DATA
Table 10-1 lists the TUSB2E11 registers. All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
70h | U_TX_ADJUST_PORT1 | RAP Register for Port 1 (0h), Default through OTP | Go |
71h | U_HS_TX_PRE_EMPHASIS_P1 | RAP Register for Port 1 (1h), Default through OTP | Go |
72h | U_RX_ADJUST_PORT1 | RAP Register for Port 1 (2h), Default through OTP | Go |
73h | U_DISCONNECT_SQUELCH_PORT1 | RAP Register for Port 1 (3h), Default through OTP | Go |
77h | E_HS_TX_PRE_EMPHASIS_P1 | RAP Register for Port 1 (7h), Default through OTP | Go |
78h | E_TX_ADJUST_PORT1 | RAP Register for Port 1 (8h), Default through OTP | Go |
79h | E_RX_ADJUST_PORT1 | RAP Register for Port 1 (9h), Default through OTP | Go |
0h | GPIO0_CONFIG | Go | |
40h | GPIO1_CONFIG | Go | |
50h | UART_PORT1 | RAP Register for Port 1 (20h) | Go |
B0h | REV_ID | Go | |
B2h | GLOBAL_CONFIG | Go | |
B3h | INT_ENABLE_1 | Go | |
B4h | INT_ENABLE_2 | Go | |
B5h | FRAME_LP_CONTROL | Controls for Frame Based LP mode | Go |
B6h | BC_CONTROL | Go | |
B7h | BC_STATUS_1 | Go | |
A3h | INT_STATUS_1 | Go | |
A4h | INT_STATUS_2 | Go | |
60h | CONFIG_PORT1 | Go | |
F5h | TEST_MODE1 | Go |
Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
H | H | Set or cleared by hardware |
R | R | Read |
RH | R H |
Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
W1C | W 1C |
Write 1 to clear |
WtoP | W | Write |
Reset or Default Value | ||
- n | Value after reset or the default value |
GPIO0_CONFIG is shown in GPIO0_CONFIG Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO0_OD_PP | R/W | 0h | GPIO0 output type 0h = open-drain output 1h = push pull output |
6 | Reserved | R | 0h | Reserved |
5 | GPIO0_DIRECTION | R/W | 0h | GPIO0 direction 0h = input 1h = output |
4 | GPIO0_INPUT_STATUS | RH | 0h | Logical value of GPIO0 pin input (0=Low, 1=High) 0h = input is low 1h = input is high |
3-0 | GPIO0_OUTPUT_SELECT | R/W | 0h |
Dh = HIGH_OUTPUT – output is forced static high Eh = LOW_OUTPUT – output is forced static low |
GPIO1_CONFIG is shown in GPIO1_CONFIG Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO1_OD_PP | R/W | 0h | GPIO1 output type selection 0h = open-drain output 1h = push pull output |
6 | GPIO1_IN_TRIGGER_TYPE | R/W | 0h | GPIO1 input trigger type selection for interrupt 0h = edge trigger input 1h = level trigger input (GPIO2 output reflects the input level state) |
5 | GPIO1_DIRECTION | R/W | 0h | GPIO1 direction selection 0h = input 1h = output |
4 | GPIO1_INPUT_STATUS | RH | 0h | Logical value of GPIO1 pin input status (0=Low, 1=High) 0h = input is low 1h = input is high |
3-0 | GPIO1_OUTPUT_SELECT | R/W | 0h | GPIO1 output selection 0h = Remote wakeup – host repeater is receiving remote wake but has not seen start of resume 1h = USB disconnect – host repeater is actively forwarding LS/FS disconnect. 2h = USB_HS_Unsquelched – host repeater in L0 seeing USB HS or in reset seeing Chirp 3h = PVTB – HOST repeater is actively transmitting ESE1 due to HS disconnect. 4h = DEFAULT – waiting to be configured host/peripheral 5h = HOST – in host repeater mode 6h = PERIPHERAL – in peripheral repeater mode 7h = CONNECTED – repeater is connected, connection seen acknowledged by start of reset 8h = RESET – reset in progress, reset is detected is high, L0 is low 9h = L0 – fully configured and repeating data, keep-alive and reset/disconnect Ah = L1 – device has received CM.FS/CM.L1,has stopped repeating and is waiting for wake or resume Bh = L2 – device has received CM.L2, has stopped repeating and is waiting for wake or resume. Ch = GPIO1_HS_TEST – in host repeater in L0 mode, received CM.TEST Dh = HIGH_OUTPUT – output is forced static high Eh = LOW_OUTPUT – output is forced static low Fh = OVP – over voltage (DP/DN voltage > VOVP_TH) detected on the USB DP/DN |
U_TX_ADJUST_PORT1 is shown in Table 10-5.
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Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | U_HS_TERM_P1 | RH/W | 1h |
0h = 42.75Ω (typical) 1h = 45Ω (typical) (default) 2h = 47.25Ω (typical) 3h = 49.5Ω (typical) |
5-4 | U_HS_TX_SLEW_RATE_P1 | RH/W | 3h |
0h = 425 ps (typical) 1h = 465 ps (typical) 2h = 510 ps (typical) 3h = 625 ps (typical) (OTP default) |
3-0 | U_HS_TX_AMPLITUDE_P1 | RH/W | Ch |
0h = 800mV – 7.5%, 740mV (typical) 1h = 800mV – 5.0%, 760mV (typical) 2h = 800mV – 2.5%, 780mV (typical) 3h = 800mV (USB 2.0 specification nominal), 800mV (typical) (B0 OTP default) 4h = 800mV + 2.5%, 820mV (typical) 5h = 800mV + 5.0%, 840mV (typical) 6h = 800mV + 7.5%, 860mV (typical) 7h = 800mV + 10%, 880mV (typical) 8h = 800mV + 12.5%, 900mV (typical) 9h = 800mV + 15%, 920mV (typical) Ah = 800mV + 17.5%, 940mV (typical) Bh = 800mV + 20%, 960mV (typical) Ch = 800mV + 22.5%, 980mV (typical) (B1 OTP default) Dh = 800mV + 25%, 1000mV (typical) Eh = 800mV + 27.5%, 1020mV (typical) Fh = 800mV + 30%, 1040mV (typical) |
U_HS_TX_PRE_EMPHASIS_P1 is shown in Table 10-6.
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Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CDP_2_EN_P1 | RH/W | 0h | 0h = CDP advertising disabled 1h = CDP advertising enabled |
6 | Reserved | RH/W | 0h | Reserved |
5-4 | U_HS_TX_PE_WIDTH_P1 | RH/W | 3h |
0h = 0.35 UI (typical) 1h = 0.45 UI (typical) 2h = 0.55 UI (typical) 3h = 0.65 UI (typical) (OTP default) |
3 | U_HS_TX_PE_ENABLE_P1 | RH/W | 1h | USB HS TX pre-emphasis enable Default through OTP PE is disabled during chirp J (VCHIRPJ) or chirp K (VCHIRPK) 0h = Disabled 1h = Enabled (OTP default) |
2-0 | U_HS_TX_PRE_EMPHASIS_P1 | RH/W | 4h |
0h = 0.5dB (typical) (B0 OTP default) 1h = 0.9dB (typical) 2h = 1.2dB (typical) 3h = 1.7dB (typical) 4h = 2.1dB (typical) (B1 OTP default) 5h = 2.5dB (typical) 6h = not recommended 7h = not recommended |
U_RX_ADJUST_PORT1 is shown in Table 10-7.
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Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Reserved | RH/W | 9h | Reserved |
3 | Reserved | RH/W | 0h | Reserved |
2-0 | U_EQ_P1 | RH/W | 2h |
0h = 0.06dB (typical) (B0 OTP default) 1h = 0.58dB (typical) 2h = 1.09dB (typical) (B1 OTP default) 3h = 1.56dB (typical) 4h = 2.26dB (typical) 5h = 2.67dB (typical) 6h = 3.03dB (typical) 7h = 3.35dB (typical) |
U_DISCONNECT_SQUELCH_PORT1 is shown in Table 10-8.
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Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | U_DISCONNECT_THRESHOLD_P1 | RH/W | 8h |
0h = 525mV (minimum), 0% (B0 OTP default) 1h = 545mV (minimum), +4% 2h = 565mV (minimum), +8% 3h = 585mV (minimum), +11% 4h = 605mV (minimum), +15% 5h = 625mV (minimum), +19% 6h = 645mV (minimum), +23% 7h = 665mV (minimum), +27% 8h = 685mV (minimum) (B1 OTP default), +31% 9h = 705mV (minimum), +34% Ah = 725mV (minimum), +38% Bh = 745mV (minimum), +42% Ch = 765mV (minimum), +46% Dh = 785mV (minimum), +50% Eh = 805mV (minimum), +53% Fh = 825mV (minimum), +57% |
3 | Reserved | RH/W | 0h | Reserved |
2-0 | U_SQUELCH_THRESHOLD_P1 | RH/W | 3h |
0h = 130mV (minimum), +30% 1h = 124mV (minimum), +24% 2h = 117mV (minimum), +17% 3h = 111mV (minimum), +11% (B1 OTP default) 4h = 104mV (minimum), +4% (B0 OTP default) 5h = 98mV (minimum), −2% 6h = 91mV (minimum), −9% 7h = 85mV (minimum), −15% |
E_HS_TX_PRE_EMPHASIS_P1 is shown in Table 10-9.
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Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | E_HS_TX_PRE_EMPHASIS_P1 | RH/W | 0h |
0h = 0dB (typical) (default) 1h = 0.67dB (typical) 2h = 1.29dB (typical) 3h = 1.87dB (typical) 4h = 2.41dB (typical) 5h = 2.92dB (typical) 6h = 3.41dB (typical) 7h = 3.86dB (typical) |
4-3 | E_HS_TX_PE_WIDTH_P1 | RH/W | 0h |
0h = 0.40 UI (typical) (default) 1h = 0.5 UI (typical) 2h = 0.55 UI (typical) 3h = 0.65 UI (typical) |
2-1 | Reserved | RH/W | 0h | Reserved |
0 | BC_DETECTION_ENABLE_P1 | RH/W | 0h | Enables battery charger (BC) detection during peripheral repeater
mode. BC detection is disabled if the corresponding register is written low. Detection enable is further gated with connect announcement by SoC. After detection attempt completes, repeater enables the pull up. 0h = detection disabled. 1h = detection enabled |
E_TX_ADJUST_PORT1 is shown in Table 10-10.
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Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | RH/W | 0h | Reserved |
6 | Autoresume Disable | RH/W | 0h | Added in B1 0h = autoresume enabled 1h = autoresume disabled |
5 | Reserved | RH/W | 0h | Reserved |
4-3 | E_HS_TX_SLEW_RATE_P1 | RH/W | 1h | 0h = 390 ps (typical) 1h = 440 ps (typical) (default) 2h = 460 ps (typical) 3h = 490 ps (typical) |
2-0 | E_HS_TX_AMPLITUDE_P1 | RH/W | 3h | 0h = 360mV (typical) 1h = 380mV (typical) 2h = 400mV (typical) 3h = 420mV (typical) (default) 4h = 440mV (typical) 5h = 460mV (typical) 6h = 480mV (typical) 7h = 500mV (typical) |
E_RX_ADJUST_PORT1 is shown in Table 10-11.
Return to the Summary Table.
Hardware default value can be overridden through factory programmable OTP for this register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | RH/W | 0h | Reserved |
6-4 | E_SQUELCH_THRESHOLD_P1 | RH/W | 6h |
0h = 104mV (typical) 1h = 101mV (typical) 2h = 98mV (typical) 3h = 90mV (typical) 4h = 81mV (typical) (B0 OTP default) 5h = 73mV (typical) 6h = 67mV (typical) (B1 OTP default) 7h = 60mV (typical) |
3-0 | E_EQ_P1 | RH/W | 0h |
0h = 0.34dB (typical) (default) 1h = 0.71dB (typical) 2h = 1.02dB (typical) 3h = 1.36dB (typical) 4h = 1.64dB (typical) 5h = 1.94dB (typical) 6h = 2.19dB (typical) 7h = 2.45dB (typical) 8h = 2.69dB (typical) 9h = 2.93dB (typical) Ah = 3.13dB (typical) Bh = 3.35dB (typical) Ch = 3.53dB (typical) Dh = 3.72dB (typical) Eh = 3.89dB (typical) Fh = 4.07dB (typical) |
UART_PORT1 is shown in Table 10-12.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | Reserved | R/W | 0h | Reserved |
4 | uart_cross_P1 | R/W | 0h | Select whether plus and minus pins are crossed between USB 2.0 and
eUSB2 during UART mode 0h = if UART mode is enabled, pair eD+ with D+ and eD- with D- 1h = if UART mode is enabled, pair eD+ with D- and eD- with D+ |
3 | UART_use_bit1_P1 | R/W | 0h | Select whether UART enable select is set by register bit 1 or not
0h = bit 1 ignored. UART mode enabled by GPIO0 1h = bit 1 (UART_en_by_reg_not_pin_P1) enabled |
2 | UART_dir_not_Carkit_P1 | R/W | 0h | Set UART mode, direction, low for Carkit and high for opposite 0h = UART mode uses Carkit directions, D+ to eUSB2 and eD- to USB 2.0 1h = UART mode directions are opposite of Carkit, D- to eUSB2 and eD+ to USB 2.0 |
1 | UART_en_by_reg_not_pin_P1 | R/W | 1h | Select whether Carkit UART mode is enabled by register or by GPIO0
pin 0h = select GPIO0 pin to enable UART mode 1h = select UART_mode_en_P1 register to enable UART mode |
0 | UART_mode_en_P1 | R/W | 0h | If GPIO0 is not selected to enable Carkit UART mode, this register
enables the Carkit UART mode. 0h = disable UART mode between eUSB2 and USB 2.0 pins 1h = enable UART mode between eUSB2 and USB 2.0 pins |
REV_ID is shown in Table 10-13.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REV_ID | RH | 02h | Device revision. 01h = A0 02h = B0 03h = B1 |
GLOBAL_CONFIG is shown in Table 10-14.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SOFT_RST | HWtoP | 0h | Writing a 1 to this field is equivalent to pulsing RESETB low |
6 | DISABLE_P1 | R/W | 0h | Disabled Mode Repeater 1 (I2C remains Active) (If port is not disconnected, wait until disconnect event to disable the repeater) 0h = repeater enabled 1h = repeater disabled |
5 | Reserved | R | 0h | Reserved |
4 | GPIO2_OUT_TYPE | R/W | 0h | GPIO2 output type 0h = open drain 1h = push-pull |
3 | GPIO2_POLARITY | R/W | 0h | GPIO2 pin polarity in push-pull mode only (open-drain mode is always
active low) 0h = active high 1h = active low |
2-0 | Reserved | R | 0h | Reserved |
INT_ENABLE_1 is shown in INT_ENABLE_1 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO1_RISING_EDGE | R/W | 0h | INT_GPIO1_RISING_EDGE enable. When GPIO1_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt on Rising Edge of GPIO1. When GPIO1_IN_TRIGGER_TYPE = 1 (Level), this enables interrupt when GPIO1 = High. 0h = not enabled 1h = enabled |
6 | GPIO1_FALLING_EDGE | R/W | 0h | INT_GPIO1_FALLING_EDGE enable. When GPIO1_IN_TRIGGER_TYPE = 0 (Edge), this enables interrupt on Falling Edge of GPIO1. When GPIO1_IN_TRIGGER_TYPE = 1 (Level), this enables interrupt when GPIO1 = Low. 0h = not enabled 1h = enabled |
5 | Reserved | R | 0h | Reserved |
4 | Reserved | R | 0h | Reserved |
3 | USB_REMOTE_WAKE_P1 | R/W | 0h | INT_USB_REMOTE_WAKE_P1 enable. See Section 8.4.6 0h = not enabled 1h = enabled |
2 | USB_DISCONNECT_P1 | R/W | 0h | INT_USB_DISCONNECT_P1 enable. See Section 8.4.6 0h = not enabled 1h = enabled |
1 | Reserved | R | 0h | Reserved |
0 | Reserved | R | 0h | Reserved |
INT_ENABLE_2 is shown in INT_ENABLE_2 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_OVERRIDE_EN | R/W | 0h | Override GPIO2 INT output 0h = not enabled 1h = enabled See INT_VALUE |
6 | INT_VALUE | R/W | 0h | Value to drive on GPIO2 when INT_OVERRIDE_EN=1 GPIO2 output pin indicates the interrupt assertion. The GPIO2 output pin follows the GPIO2 pin configuration. In open-drain mode the GPIO2 output pin is active low to indicate interrupt assertion. In push-pull mode, the GPIO2 output pin follows active low/high configuration to indicate GPIO2 assertion. 0h = output: interrupt not asserted 1h = output: interrupt asserted |
5 | BC_CHG_DET_P1 | R/W | 0h | INT_BC_CHG_DET_P1 enable. 0h = not enabled 1h = enabled |
4 | Reserved | R | 0h | Reserved |
3 | USB_DETECT_ATTACH_P1 | R/W | 0h | INT_USB_DET_ATTACH_P1 enable. Enable device attach detection while eDSP is powered down See Section 8.4.7 0h = not enabled 1h = enabled |
2 | Reserved | R | 0h | Reserved |
1 | USB_OVP_P1 | R/W | 0h | Over Voltage Port 1 interrupt enable 0h = not enabled 1h = enabled |
0 | Reserved | R | 0h | Reserved |
BC_CONTROL is shown in Table 10-17.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | HOST_FRAME_LP_EN | RH/W | 1h | Host repeater frame-based low power enable. Default via OTP 0 = Not Enabled 1 = Enabled |
6 | DEVICE_FRAME_LP_EN | RH/W | 0h | Peripheral repeater frame-based low power enable. Default via OTP 0 = Not Enabled 1 = Enabled |
5 | Reserved | R | 1h | Reserved |
4 | Reserved | R | 0h | Reserved |
3-2 | FRAME_LP_OFF_THRESHOLD | RH/W | 0h | Idle duration as a fraction of frame length until Frame-based Low
Power state entered Default via OTP 0h = 1/32 1h = 1/16 2h = 1/8 3h = 1/4 |
1 | IDLE_LP_EN | RH/W | 1h | Enable response-based low power mode Default via OTP 0h = Not enabled 1h = Enabled |
0 | Reserved | R | 0h | Reserved |
BC_CONTROL is shown in BC_CONTROL Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | i2c_ds_config | RH/W | 3h | I2C open-drain output drive strength selection This is intended to be set through I2C. 0h ≅1mA (typical) 1h ≅2mA (typical) 2h ≅4mA (typical) 3h ≅8mA (typical) (default) |
5-4 | DEFAULT_STATE_BC_P1 | RH/W | 0h | Battery charger advertisement or detection selected for default
state of eUSB2 repeater 0h = neither detect nor advertise charger 1h = detect charger starting when GPIO1 goes high. 2h = advertise short mode DCP. DCP is 1.2V if 1P2V_MODE is '1' else pure BC 1.2 DCP 3h = auto-cycle ACP3 to short mode DCP. Short mode passes through 1.2V DCP for 12 seconds prior to pure BC 1.2 DCP if 1P2V_MODE is '1' |
3 | VBUS_CONTROL_POLARITY | RH/W | 0h | Select polarity of VBUS control output pin 0h = active high 1h = active low |
2 | 1P2V_MODE_DIS | RH/W | 0h | Disable advertising 1.2V mode in default state whether enabled to
auto-cycle or not 0h = 1.2V mode enabled 1h = 1.2V mode disabled |
1 | INT_PIN_FUNCTION | RH/W | 0h | Select function of GPIO2 pin in I2C mode 0h = INT (interrupt) 1h = CHG_DET (Charger Detected) |
0 | CHG_DET_POLARITY | RH/W | 0h | Select polarity of CHG_DET I2C mode status output pin 0h = active low 1h = active high |
BC_STATUS_1 is shown in BC_STATUS_1 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | RH | 0h | Reserved |
6-4 | CHARGER_TYPE_DET_P1 | RH | 0h | Type of battery charger detected on Port 1 0h = SDP – 500mA 1h = divider 0 – 500mA 2h = divider 1 – 1 A 3h = CDP – 1.5 A 4h = BC 1.2 DCP – 1.5 A 5h = 1.2V pullup and short – 2 A 6h = divider 2 – 2.1 A 7h = divider 3 – 2.4 A |
3 | Reserved | RH | 0h | Reserved |
2-0 | Auto_DCP_STATE_P1 | RH | 0h | State of auto-DCP sequence on Port 1 0h = no advertisement 5h = divider 3 (2.4 A) 6h = 1.2V pullup and short 7h = BC 1.2 DCP |
INT_STATUS_1 is shown in INT_STATUS_1 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_GPIO1_RISING_EDGE | R/W1C | 0h | GPIO1 Rising Edge enable 0h = no interrupt 1h = interrupt |
6 | INT_GPIO1_FALLING_EDGE | R/W1C | 0h | GPIO1 Falling Edge enable 0h = no interrupt 1h = interrupt |
5 | Reserved | R | 0h | Reserved |
4 | Reserved | R | 0h | Reserved |
3 | INT_USB_REMOTE_WAKE_P1 | R/W1C | 0h | Remote Wake Event Detect on USB Port 1 See Section 8.4.6 0h = no interrupt 1h = interrupt |
2 | INT_USB_DISCONNECT_P1 | R/W1C | 0h | Disconnect event has occurred on Port 1 See Section 8.4.6 0h = no interrupt 1h = interrupt |
1-0 | Reserved | R | 0h | Reserved |
INT_STATUS_2 is shown in INT_STATUS_2 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | Reserved | R | 0h | Reserved |
5 | INT_BC_CHG_DET_P1 | R/W1C | 0h | Detected battery charger on Port 1 0h = no interrupt 1h = interrupt |
4 | Reserved | R | 0h | Reserved |
3 | INT_USB_DET_ATTACH_P1 | R/W1C | 0h | Device Attach event has occurred on Port 1 See Section 8.4.7
0h = no interrupt 1h = interrupt |
2 | Reserved | R | 0h | Reserved |
1 | INT_USB_OVP_P1 | R/W1C | 0h | Over voltage condition has occurred (DP/DN) 0h = no interrupt 1h = interrupt |
0 | Reserved | R | 0h | Reserved |
CONFIG_PORT1 is shown in CONFIG_PORT1 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | Reserved | R | 0h | Reserved |
4-3 | HOST_DEVICE_P1 | RH | 0h | Port1 is configured as a Host repeater or a Device repeater 0h = not configured 1h = host repeater 2h = device repeater 3h = reserved |
2-1 | Reserved | R | 0h | Reserved |
0 | CDP_2_STATUS_P1 | RH | 0h | Primary detection detected on port1 if CDP_2_EN_P1=1 0h = CDP primary detection detected 1h = CDP primary detection not detected |
TEST_MODE1 is shown in TEST_MODE1 Register Field Descriptions.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Reserved | R/W | 0h | Reserved, make sure to rewrite what was read |
3 | FORCE_HS_L0 | R/W | 0h | Force repeater into high-speed L0 state for test purposes only. 0h = normal repeater mode (setting this bit to 0 does not return the device to normal repeater mode, the device required a hard reset, soft reset or power cycled) 1h = forced high-speed L0 mode |
2-0 | Reserved | R/W | Xh | Variant ID. 00h = 1.2V I/O 02h = 1.8V I/O Must not change the value, rewrite the value that is read. |