SNLS648C February   2019  – August 2024 TUSB2E22

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
  7. 6 Parametric Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 2.0
      2. 7.3.2 eUSB2
      3. 7.3.3 Cross MUX
    4. 7.4 Device Functional Modes
      1. 7.4.1 Repeater Mode
      2. 7.4.2 Power Down Mode
      3. 7.4.3 CROSS
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Dual Port System Implementation
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up Reset
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Example YCG Layout For Application With No Cross MUX Function.
      3. 8.4.3 Example RZA Layout For Application With No Cross MUX Function
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RZA|20
  • YCG|25
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Timing Requirements

MIN NOM MAX UNIT
RESET TIMING
t_VDD1V8_RAMP Ramp time for VDD1V8 to reach minimum 1.62 V 2 ms
t_VDD3V3_RAMP Ramp time for VDD3V3 to reach minimum 3.0 V 2 ms
t_su_CROSS Setup time for CROSS sampled at the deassertion of RESETB 0 ms
t_hd_CROSS Hold time for CROSS sampled at the deassertion of RESETB 3 ms
t_aRESETB duration for RESETB to be asserted low to complete reset while powered 10 us
t_RH_READY Time for eUSB2 interface to be ready after RESETB is deasserted or (VDD1V8 and VDD3V3) reach minimum recommended voltages, whichever is later  3 ms