SNLS757B June 2024 – November 2024 TUSB2E221
PRODMIX
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
I/O TIMING | |||||
t_GPIO_PW | Minimum GPIO pulse width for INT event | 8 | µs | ||
RESET TIMING | |||||
t_VDD1V8_RAMP | Ramp time for VDD1V8 to reach minimum 1.62V | 2 | ms | ||
t_VDD3V3_RAMP | Ramp time for VDD3V3 to reach minimum 3.0V | 2 | ms | ||
t_su_CROSS | Setup time for CROSS sampled at the deassertion of RESETB | 0 | ms | ||
t_hd_CROSS | Hold time for CROSS sampled at the deassertion of RESETB | 3 | ms | ||
t_aRESETB | Duration for RESETB to be asserted low to complete reset while powered | 10 | µs | ||
t_RH_READY | Time for device to be ready to accept RAP and I2C requests and eUSB2 interface to be ready after RESETB is deasserted or (VDD1V8 and VDD3V3) reach minimum recommended voltages, whichever is later | 3 | ms | ||
t_RS_READY | Time for device to be ready to accept RAP and I2C requests and eUSB2 interface to be ready after soft reset through I2C | 350 | µs | ||
REPEATER TIMING | |||||
TJ1E | Total additive jitter for eUSB2 to USB 2.0 (output jitter - input jitter) of repeater when one of the two repeater is disabled. (must also include all complete SOP bits and measured with eUSB2 TX rise/fall time skew and intra-pair prop delay skew, refer to VCM_RX_AC) [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel]. Egress setup diagram | 25 | 42 | ps | |
TJ1I | Total additive jitter for USB to eUSB2 (output jitter - input jitter) of repeater when one of the two repeater is disabled. [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel]. Ingress setup diagram | 25 | 42 | ps | |
TJ2E | Total additive jitter for eUSB2 to USB (output jitter - input jitter) of repeater when both repeaters are active. [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel] | 60 | ps | ||
TJ2I | Total additive jitter for USB to eUSB2 (output jitter - input jitter) of repeater when both repeaters are active. [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel] | 60 | ps | ||
Te_to_U_DJ1 |
eUSB2 to USB 2.0 repeater FS jitter to next transition (Per eUSB2 spec 1.1 Table 7-13 Note 1 & 2 condition for Supply and GND delta (1)) | –6.0 |
+6.0 |
ns | |
TU_to_e_DJ1 |
USB 2.0 to eUSB2 repeater FS jitter to next transition (Per eUSB2 spec 1.1 Table 7-13 Note1 & 2 condition for Supply and GND delta (1)) | –3.0 |
+3.0 |
ns | |
TDJ2_e2U |
Repeater FS paired transition jitter in eUSB2 to USB 2.0 direction (Relaxed relative to THDJ2 defined by USB 2.0 +/-1ns) | –1.5 |
+1.5 |
ns | |
TDJ2_U2e |
Repeater FS paired transition jitter in USB 2.0 to eUSB2 direction (Relaxed relative to THDJ2 defined by USB 2.0 +/-1ns) | –1.5 |
+1.5 |
ns | |
MODE TIMING | |||||
TMODE_SWITCH | Time needed to change mode from UART bypass mode to and from USB mode | 1 | µs | ||
TUART_START | Time needed to start transmitting UART data after entering UART bypass mode | 2 | ms | ||
I2C (FM+) | |||||
tSU_STA | Start setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ | 260 | ns | ||
tSU_STO | Stop setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ | 260 | ns | ||
tHD_STA | Start hold time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ | 260 | ns | ||
tSU_DAT | Data input or False start/stop, setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ | 50 | ns | ||
tHD_DAT | Data input or False start/stop, hold time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ | 0 | ns | ||
tVD_DAT, tVD_ACK | SDA output delay, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ | 20 | 450 | ns | |
tHD_DAT_SL | Data hold time when device is transmitting | 6.67 | ns | ||
tSP | Glitch width suppressed | 50 | 91 | ns | |
tBUF | Bus free time between a STOP and START condition (host minimum spec that device must tolerate) | 0.5 | µs | ||
tLOW | Low Period for SCL clock (host minimum spec that device must tolerate) | 0.5 | µs | ||
tHIGH | High Period for SCL clock (host minimum spec that device must tolerate) | 0.26 | µs | ||
I2C (FM) | |||||
tSU_STO | Stop setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM | 600 | ns | ||
tHD_STA | Start hold time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM | 600 | ns | ||
tSU_STA | Start setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM | 600 | ns | ||
tSU_DAT | Data input or False start/stop, setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM | 100 | ns | ||
tHD_DAT | Data input or False start/stop, hold time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM | 0 | ns | ||
tVD_DAT, tVD_ACK | SDA output delay, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM | 20 | 900 | ns | |
tHD_DAT_SL | Data hold time when device is transmitting | 13.5 | ns | ||
tSP | Glitch width suppressed | 50 | 91 | ns | |
tBUF | Bus free time between a STOP and START condition (host minimum spec that device must tolerate) | 1.3 | µs | ||
tLOW | Low Period for SCL clock (host minimum spec that device must tolerate) | 1.3 | µs | ||
tHIGH | High Period for SCL clock (host minimum spec that device must tolerate) | 0.6 | µs | ||
I2C (STD) | |||||
tSU_STO | Stop setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD | 4 | µs | ||
tHD_STA | Start hold time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD | 4 | µs | ||
tSU_STA | Start setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD | 4.7 | µs | ||
tSU_DAT | Data input or False start/stop, setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD | 250 | ns | ||
tHD_DAT | Data input or False start/stop, hold time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD | 5 | µs | ||
tVD_DAT, tVD_ACK | SDA output delay, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD | 3.45 | µs | ||
tHD_DAT_SL | Data hold time when device is transmitting | 13.5 | ns | ||
tSP | Glitch width suppressed | 50 | 91 | ns | |
tBUF | Bus free time between a STOP and START condition (host minimum spec that device must tolerate) | 4.7 | µs | ||
tLOW | Low Period for SCL clock (host minimum spec that device must tolerate) | 4.7 | µs | ||
tHIGH | High Period for SCL clock (host minimum spec that device must tolerate) | 4.0 | µs |