The TUSB322I device enables USB Type-C ports with the configuration channel (CC) logic required for Type-C ecosystems. The TUSB322I device uses the CC pins to determine port attach and detach, cable orientation, role detection, and port control for Type-C current mode. The TUSB322I device can be configured as a downstream facing port (DFP), upstream facing port (UFP), or a dual role port (DRP), making the TUSB322I device ideal for any application.
The TUSB322I device alternates configuration as a DFP or UFP according to the Type-C Specifications. The CC logic block monitors the CC1 and CC2 pins for pullup or pulldown resistances to determine when a USB port has been attached, the orientation of the cable, and the role detected. The CC logic detects the Type-C current mode as default, medium, or high depending on the role detected. VBUS detection is implemented to determine a successful attach in UFP and DRP modes. The TUSB322I will supply VCONN when an active cable is detected.
The device operates over a wide supply range and has low-power consumption. The TUSB322I device is available in industrial temperature ranges.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TUSB322I | X2QFN (12) | 1.60 mm × 1.60 mm |
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Changes from B Revision (September 2016) to C Revision
Changes from A Revision (May 2016) to B Revision
Changes from * Revision (October 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CC1 | 1 | I/O | Type-C configuration channel signal 1 |
CC2 | 2 | I/O | Type-C configuration channel signal 2 |
VBUS_DET | 3 | I | 5-V to 28-V VBUS input voltage. VBUS detection determines UFP attachment. One 900-kΩ external resistor required between system VBUS and VBUS_DET pin. |
DIR | 4 | O | DIR of plug. The open drain output indicates the detected plug orientation: Type-C plug position 2 (H); Type-C plug position 1 (L). |
ADDR | 5 | I | Tri-level input pin to indicate I2C address or GPIO mode: H - I2C is enabled and I2C 7-bit address is 0x67. NC - GPIO mode (I2C is disabled) L - I2C is enabled and I2C 7-bit address is 0x47. ADDR pin should be pulled up to VDD if high configuration is desired |
INT_N/OUT3 | 6 | O | The INT_N/OUT3 is a dual-function pin. When used as the INT_N, the pin is an open drain output in I2C control mode and is an active low interrupt signal for indicating changes in I2C registers. When used as OUT3, the pin is in audio accessory detect in GPIO mode: no detection (H), audio accessory connection detected (L). |
SDA/OUT1 | 7 | I/O | The SDA/OUT1 is a dual-function pin. When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication data signal. When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the TUSB322I device is in UFP mode: default current mode detected (H); medium or high current mode detected (L). |
SCL/OUT2 | 8 | I/O | The SCL/OUT2 is a dual function pin. When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication clock signal. When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C current mode detect when the TUSB322I device is in UFP mode: default or medium current mode detected (H); high current mode detected (L). |
ID | 9 | O | Open drain output; asserted low when the CC pins detect device attachment when port is a source (DFP), or dual-role (DRP) acting as source (DFP). |
GND | 10 | G | Ground |
EN_N | 11 | I | EN_N. Active low enable. |
VDD | 12 | P | Positive supply voltage |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD | Supply voltage | 4.5 | 5 | 5.5 | V | |
VBUS | System VBUS voltage | 4 | 5 | 28 | V | |
VCONTROL | DC voltage range for control lines: ADDR, ID, DIR, INT_N/OUT3, SDA/OUT1, SCL/OUT2, EN_N, CC1, and CC2. | 0 | 5.5 | V | ||
DC voltage range for VBUSDET | 0 | 4 | V | |||
VCONN | Supply for active cable (With VDD at 5 V) | 4.75 | 5.5 | V | ||
TA | Operating free-air temperature | TUSB322I | –40 | 25 | 85 | °C |
THERMAL METRIC(1) | TUSB322I | UNIT | |
---|---|---|---|
RWB (X2QFN) | |||
12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 169.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 68.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 83.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 2.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 83.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Power Consumption | ||||||
ISHUTDOWN_UFP | Leakage current when VDD is supplied but the device is not enabled. (VDD = 5 V, EN_N = H) | 0.04 | µA | |||
IUNATTACHED_UFP | Current consumption in unattached mode when port is unconnected and waiting for connection. (VDD = 5 V, ADDR = NC, MODE_SELECT = 2'b01) | 70 | µA | |||
IACTIVE_UFP | Current consumption in active mode. (VDD = 5 V, ADDR = NC, MODE_SELECT = 2'b01) | 70 | µA | |||
CC1 and CC2 Pins | ||||||
RCC_DB | Pulldown resistor when in dead-battery mode. | 4.1 | 5.1 | 6.1 | kΩ | |
RCC_D | Pulldown resistor when in UFP or DRP mode. | 4.6 | 5.1 | 5.6 | kΩ | |
VUFP_CC_USB | Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability. | 0.25 | 0.61 | V | ||
VUFP_CC_MED | Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5 A) current source capability. | 0.7 | 1.16 | V | ||
VUFP_CC_HIGH | Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising high (3 A) current source capability. | 1.31 | 2.04 | V | ||
VTH_DFP_CC_USB | Voltage threshold for detecting a UFP attach when configured as a DFP and advertising default current source capability. | 1.51 | 1.6 | 1.64 | V | |
VTH_DFP_CC_MED | Voltage threshold for detecting a UFP attach when configured as a DFP and advertising medium current (1.5 A) source capability. | 1.51 | 1.6 | 1.64 | V | |
VTH_DFP_CC_HIGH | Voltage threshold for detecting a UFP attach when configured as a DFP and advertising high current (3.0 A) source capability. | 2.46 | 2.6 | 2.74 | V | |
VTH_AC_CC_USB | Voltage threshold for detecting a active cable attach when configured as a DFP and advertising default current source. | 0.15 | 0.2 | 0.25 | V | |
VTH_AC_CC_MED | Voltage threshold for detecting a active cable attach when configured as a DFP and advertising medium current (1.5 A) source. | 0.35 | 0.4 | 0.45 | V | |
VTH_AC_CC_HIGH | Voltage threshold for detecting a active cable attach when configured as a DFP and advertising high current (3.0 A) source. | 0.76 | 0.8 | 0.84 | V | |
ICC_DEFAULT_P | Default mode pullup current source when operating in DFP or DRP mode. | 64 | 80 | 96 | µA | |
ICC_MED_P | Medium (1.5 A) mode pullup current source when operating in DFP or DRP mode. | 166 | 180 | 194 | µA | |
ICC_HIGH_P | High (3 A) mode pullup current source when operating in DFP or DRP mode.(1) | 304 | 330 | 356 | µA | |
Control Pins: EN_N, ADDR, INT/OUT3, DIR, ID | ||||||
VIL | Low-level control signal input voltage, (EN_N, ADDR) | 0.4 | V | |||
VIM | Mid-level control signal input voltage (ADDR) | 0.28 × VDD | 0.56 × VDD | V | ||
VIH | High-level control signal input voltage (EN_N, ADDR) | VDD – 0.3 | VDD | V | ||
IIH | High-level input current | –20 | 20 | µA | ||
IIL | Low-level input current | –10 | 10 | µA | ||
IID_LEAKAGE | Current leakage on ID pin. | VDD = 0 V; ID = 5 V | 10 | µA | ||
REN_N | Internal pull-up resistance for EN_N. | 1.1 | MΩ | |||
Rpu | Internal pullup resistance (ADDR) | 588 | kΩ | |||
Rpd | Internal pulldown resistance (ADDR) | 1.1 | MΩ | |||
VOL | Low-level signal output voltage (open-drain) (INT_N/OUT3, ID) | IOL = –1.6 mA | 0.4 | V | ||
Rp_ODext | External pullup resistor on open drain IOs (INT_N/OUT3, ID) | 200 | kΩ | |||
Rp_TLext | Tri-level input external pullup resistor (ADDR) | 4.7 | kΩ | |||
I2C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%) when ADDR pin is low or high. (2) | ||||||
VDD_I2C | Supply range for I2C (SDA/OUT1, SCL/OUT2) | 1.65 | 1.8 | 3.6 | V | |
VIH | High-level signal voltage | 1.05 | V | |||
VIL | Low-level signal voltage | 0.4 | V | |||
VOL | Low-level signal output voltage (open drain) | IOL = –1.6 mA | 0.4 | V | ||
VBUS_DET IO Pins (Connected to System VBUS signal) | ||||||
VBUS_THR | VBUS threshold range | 2.95 | 3.3 | 3.8 | V | |
RVBUS | External resistor between VBUS and VBUS_DET pin | 855 | 887 | 920 | KΩ | |
RVBUS_PD | Internal pulldown resistance for VBUS_DET | 95 | KΩ | |||
DIR pin (Open Drain IO) | ||||||
VOL | Low-level signal output voltage | IOL = –1.6 mA | 0.4 | V | ||
VCONN | ||||||
RON | On resistance of the VCONN power FET | 1.25 | Ω | |||
VTOL | Voltage tolerance on VCONN power FET | 5.5 | V | |||
VPASS | Voltage to pass through VCONN power FET | 5.5 | V | |||
IVCONN | VCONN current limit; VCONN is disconnected above the value | 225 | 300 | 375 | mA | |
CBULK | Bulk capacitance on VCONN; placed on VDD supply | 10 | 200 | uF |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
I2C (SDA, SCL) | |||||
tSU:DAT | Data setup time | 100 | ns | ||
tHD;DAT | Data hold time | 10 | ns | ||
tSU:STA | Set-up time, SCL to start condition | 0.6 | µs | ||
tHD:STA | Hold time, (repeated) start condition to SCL | 0.6 | µs | ||
tSU:STO | Set up time for stop condition | 0.6 | µs | ||
tVD;DAT | Data valid time | 0.9 | µs | ||
tVD;ACK | Data valid acknowledge time | 0.9 | µs | ||
tBUF | Bus free time between a stop and start condition | 1.3 | µs | ||
fSCL | SCL clock frequency; I2C mode for local I2C control | 400 | kHz | ||
tr | Rise time of both SDA and SCL signals | 300 | ns | ||
tf | Fall time of both SDA and SCL signals | 300 | ns | ||
CBUS_100KHZ | Total capacitive load for each bus line when operating at ≤ 100 KHz | 400 | pF | ||
CBUS_400KHZ | Total capacitive load for each bus line when operating at 400 KHz. | 100 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCCCB_DEFAULT | Power on default of CC1 and CC2 voltage debounce time | DEBOUNCE register = 2'b00 | 168 | ms | ||
tVBUS_DB | Debounce of VBUS_DET pin after valid VBUS_THR | 2 | ms | |||
tDRP_DUTY_CYCLE | Power-on default of percentage of time DRP advertises DFP during a TDRP | DRP_DUTY_CYCLE register = 2'b00 | 30% | |||
tDRP | The period TUSB322I in DFP mode completes a DFP to UFP and back advertisement. | 50 | 75 | 100 | ms | |
tI2C_EN | Time from EN_N low and VDD active to I2C access available | 100 | ms | |||
tSOFT_RESET | Soft reset duration | 26 | 49 | 95 | ms |