SLLSEO5C October   2015  – May 2017 TUSB322I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Cables, Adapters, and Direct Connect Devices
        1. 7.3.1.1 USB Type-C Receptacles and Plugs
        2. 7.3.1.2 USB Type-C Cables
        3. 7.3.1.3 Legacy Cables and Adapters
        4. 7.3.1.4 Direct Connect Devices
        5. 7.3.1.5 Audio Adapters
      2. 7.3.2 Port Role Configuration
        1. 7.3.2.1 Downstream Facing Port (DFP) - Source
        2. 7.3.2.2 Upstream Facing Port (UFP) - Sink
        3. 7.3.2.3 Dual Role Port (DRP)
      3. 7.3.3 Type-C Current Mode
      4. 7.3.4 Accessory Support
        1. 7.3.4.1 Audio Accessory
        2. 7.3.4.2 Debug Accessory
      5. 7.3.5 I2C and GPIO Control
      6. 7.3.6 VBUS Detection
      7. 7.3.7 Cable Orientation and External MUX Control
      8. 7.3.8 VCONN Support for Active Cables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Shutdown Mode
      4. 7.4.4 Dead Battery Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 CSR Registers
        1. 7.6.1.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
        2. 7.6.1.2 Connection Status Register (offset = 0x08) [reset = 0x00]
        3. 7.6.1.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
        4. 7.6.1.4 General Control Register (offset = 0x0A) [reset = 0x00]
        5. 7.6.1.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DRP in I2C Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DFP in I2C Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 UFP in I2C Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
Control pins ADDR, ID, DIR, INT_N/OUT3, EN_N –0.3 VDD + 0.3 V
CC1, CC2 –0.3 6
SDA/OUT1, SCL/OUT2 –0.3 VDD + 0.3
VBUS_DET –0.3 4
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 4.5 5 5.5 V
VBUS System VBUS voltage 4 5 28 V
VCONTROL DC voltage range for control lines: ADDR, ID, DIR, INT_N/OUT3, SDA/OUT1, SCL/OUT2, EN_N, CC1, and CC2. 0 5.5 V
DC voltage range for VBUSDET 0 4 V
VCONN Supply for active cable (With VDD at 5 V) 4.75 5.5 V
TA Operating free-air temperature TUSB322I –40 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) TUSB322I UNIT
RWB (X2QFN)
12 PINS
RθJA Junction-to-ambient thermal resistance 169.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 68.1 °C/W
RθJB Junction-to-board thermal resistance 83.4 °C/W
ψJT Junction-to-top characterization parameter 2.2 °C/W
ψJB Junction-to-board characterization parameter 83.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Consumption
ISHUTDOWN_UFP Leakage current when VDD is supplied but the device is not enabled. (VDD = 5 V, EN_N = H) 0.04 µA
IUNATTACHED_UFP Current consumption in unattached mode when port is unconnected and waiting for connection. (VDD = 5 V, ADDR = NC, MODE_SELECT = 2'b01) 70 µA
IACTIVE_UFP Current consumption in active mode. (VDD = 5 V, ADDR = NC, MODE_SELECT = 2'b01) 70 µA
CC1 and CC2 Pins
RCC_DB Pulldown resistor when in dead-battery mode. 4.1 5.1 6.1 kΩ
RCC_D Pulldown resistor when in UFP or DRP mode. 4.6 5.1 5.6 kΩ
VUFP_CC_USB Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability. 0.25 0.61 V
VUFP_CC_MED Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5 A) current source capability. 0.7 1.16 V
VUFP_CC_HIGH Voltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising high (3 A) current source capability. 1.31 2.04 V
VTH_DFP_CC_USB Voltage threshold for detecting a UFP attach when configured as a DFP and advertising default current source capability. 1.51 1.6 1.64 V
VTH_DFP_CC_MED Voltage threshold for detecting a UFP attach when configured as a DFP and advertising medium current (1.5 A) source capability. 1.51 1.6 1.64 V
VTH_DFP_CC_HIGH Voltage threshold for detecting a UFP attach when configured as a DFP and advertising high current (3.0 A) source capability. 2.46 2.6 2.74 V
VTH_AC_CC_USB Voltage threshold for detecting a active cable attach when configured as a DFP and advertising default current source. 0.15 0.2 0.25 V
VTH_AC_CC_MED Voltage threshold for detecting a active cable attach when configured as a DFP and advertising medium current (1.5 A) source. 0.35 0.4 0.45 V
VTH_AC_CC_HIGH Voltage threshold for detecting a active cable attach when configured as a DFP and advertising high current (3.0 A) source. 0.76 0.8 0.84 V
ICC_DEFAULT_P Default mode pullup current source when operating in DFP or DRP mode. 64 80 96 µA
ICC_MED_P Medium (1.5 A) mode pullup current source when operating in DFP or DRP mode. 166 180 194 µA
ICC_HIGH_P High (3 A) mode pullup current source when operating in DFP or DRP mode.(1) 304 330 356 µA
Control Pins: EN_N, ADDR, INT/OUT3, DIR, ID
VIL Low-level control signal input voltage, (EN_N, ADDR) 0.4 V
VIM Mid-level control signal input voltage (ADDR) 0.28 × VDD 0.56 × VDD V
VIH High-level control signal input voltage (EN_N, ADDR) VDD – 0.3 VDD V
IIH High-level input current –20 20 µA
IIL Low-level input current –10 10 µA
IID_LEAKAGE Current leakage on ID pin. VDD = 0 V; ID = 5 V 10 µA
REN_N Internal pull-up resistance for EN_N. 1.1 MΩ
Rpu Internal pullup resistance (ADDR) 588 kΩ
Rpd Internal pulldown resistance (ADDR) 1.1 MΩ
VOL Low-level signal output voltage (open-drain) (INT_N/OUT3, ID) IOL = –1.6 mA 0.4 V
Rp_ODext External pullup resistor on open drain IOs (INT_N/OUT3, ID) 200 kΩ
Rp_TLext Tri-level input external pullup resistor (ADDR) 4.7 kΩ
I2C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%) when ADDR pin is low or high. (2)
VDD_I2C Supply range for I2C (SDA/OUT1, SCL/OUT2) 1.65 1.8 3.6 V
VIH High-level signal voltage 1.05 V
VIL Low-level signal voltage 0.4 V
VOL Low-level signal output voltage (open drain) IOL = –1.6 mA 0.4 V
VBUS_DET IO Pins (Connected to System VBUS signal)
VBUS_THR VBUS threshold range 2.95 3.3 3.8 V
RVBUS External resistor between VBUS and VBUS_DET pin 855 887 920 KΩ
RVBUS_PD Internal pulldown resistance for VBUS_DET 95 KΩ
DIR pin (Open Drain IO)
VOL Low-level signal output voltage IOL = –1.6 mA 0.4 V
VCONN
RON On resistance of the VCONN power FET 1.25 Ω
VTOL Voltage tolerance on VCONN power FET 5.5 V
VPASS Voltage to pass through VCONN power FET 5.5 V
IVCONN VCONN current limit; VCONN is disconnected above the value 225 300 375 mA
CBULK Bulk capacitance on VCONN; placed on VDD supply 10 200 uF
(1) VDD must be 3.5 V or greater to advertise 3 A current.
(2) When using 3.3 V for I2C, customer must ensure VDD is above 3.0 V at all times.

6.6 Timing Requirements

MIN NOM MAX UNIT
I2C (SDA, SCL)
tSU:DAT Data setup time 100 ns
tHD;DAT Data hold time 10 ns
tSU:STA Set-up time, SCL to start condition 0.6 µs
tHD:STA Hold time, (repeated) start condition to SCL 0.6 µs
tSU:STO Set up time for stop condition 0.6 µs
tVD;DAT Data valid time 0.9 µs
tVD;ACK Data valid acknowledge time 0.9 µs
tBUF Bus free time between a stop and start condition 1.3 µs
fSCL SCL clock frequency; I2C mode for local I2C control 400 kHz
tr Rise time of both SDA and SCL signals 300 ns
tf Fall time of both SDA and SCL signals 300 ns
CBUS_100KHZ Total capacitive load for each bus line when operating at ≤ 100 KHz 400 pF
CBUS_400KHZ Total capacitive load for each bus line when operating at 400 KHz. 100 pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tCCCB_DEFAULT Power on default of CC1 and CC2 voltage debounce time DEBOUNCE register = 2'b00 168 ms
tVBUS_DB Debounce of VBUS_DET pin after valid VBUS_THR 2 ms
tDRP_DUTY_CYCLE Power-on default of percentage of time DRP advertises DFP during a TDRP DRP_DUTY_CYCLE register = 2'b00 30%
tDRP The period TUSB322I in DFP mode completes a DFP to UFP and back advertisement. 50 75 100 ms
tI2C_EN Time from EN_N low and VDD active to I2C access available 100 ms
tSOFT_RESET Soft reset duration 26 49 95 ms
TUSB322I tvbus_db_sllseo5.gif Figure 1. VBUS Detect and Debounce