SLLSEK3E July   2015  – September 2017 TUSB4041I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Byte N Register
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 Downstream Port 3 Implementation
        5. 9.2.2.5 Downstream Port 4 Implementation
        6. 9.2.2.6 VBUS Power Switch Implementation
        7. 9.2.2.7 Clock, Reset, and Miscellaneous
        8. 9.2.2.8 TUSB4041I Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB4041I Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TUSB4041I device is a four-port USB 2.0 hub. The device provides USB high-speed and full-speed connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream ports. When the upstream port is connected to an electrical environment that only supports high-speed connections. USB high-speed connectivity is enabled on the downstream ports. When the upstream port is connected to an electrical environment that only supports full-speed and low-speed connections. USB high-speed connectivity is disabled on the downstream ports.

8.2 Functional Block Diagram

TUSB4041I fbd_sllsek3.gif

8.3 Feature Description

8.3.1 Battery Charging Features

The TUSB4041I device provides support for USB battery charging. Battery charging support may be enabled on a per port basis through the REG_6h(batEn[3:0]).

Battery charging support includes both CDP and DCP modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 1591-2009.

In addition to standard DCP mode, the TUSB4041I device provides a mode (AUTOMODE), which automatically provides support for DCP devices and devices that support custom charging indication. When in AUTOMODE, the port automatically switches between a divider mode and the DCP mode depending on the portable device connected. The divided mode places a fixed DC voltage on the ports DP and DM signals, which allows some devices to identify the capabilities of the charger. The default divider mode indicates support for up to 10 W. The divider mode can be configured to report a legacy current setting (up to 5 W) through REG_Ah(HiCurAcpModeEn).

The battery charging mode for each port is dependent on the state of Reg_6h(batEn[n]), the status of the VBUS input, and the state of REG_Ah(autoModeEnz) upstream port as identified in Table 1.

Table 1. TUSB4041I Battery Charging Modes

batEn[n] VBUS autoModeEnz BC MODE PORT x
(x = n + 1)
0 Don’t care Don’t care Don’t Care
1 <4 V 0 Automode(3)(4)
1 DCP(1)(2)
>4 V Don’t care CDP(1)
(1) Attached USB device is USB battery-charging specification revision 1.2 compliant
(2) Chinese Telecommunications Industry Standard YD/T 1591-2009
(3) Auto-mode automatically selects divider-mode or DCP mode.
(4) Divider mode can be configured for legacy current mode through register settings.

8.3.2 USB Power Management

The TUSB4041I device can be configured for power-switched applications using either per-port or ganged power-enable controls and overcurrent status inputs.

Power switch support is enabled by REG_5h(fullPwrMgmtz), and the per-port or ganged mode is configured by REG_5h(ganged).

The TUSB4041I device supports both active-high and active-low power-enable controls. The PWRCTL[4:1] polarity is configured by REG_Ah(pwrctlPol).

8.3.3 One-Time Programmable Configuration

The TUSB4041I device allows device configuration through one-time programmable (OTP) non-volatile memory. The programming of the OTP is supported using vendor-defined USB device requests. Contact TI for details using the OTP features

Table 2 lists features that can be configured using the OTP.

Table 2. OTP Configurable Features

CONFIGURATION REGISTER OFFSET BIT FIELD DESCRIPTION
REG_01h [7:0] Vendor ID LSB
REG_02h [7:0] Vendor ID MSB
REG_03h [7:0] Product ID LSB
REG_04h [7:0] Product ID MSB
REG_07h [0] Port-removable configuration for downstream ports 1. OTP configuration is inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
REG_07h [1] Port-removable configuration for downstream ports 2. OTP configuration is inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
REG_07h [2] Port-removable configuration for downstream ports 3. OTP configuration is inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
REG_07h [3] Port-removable configuration for downstream ports 4. OTP configuration is inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.
REG_0Ah [3] Enable device attach detection
REG_0Ah [4] High-current divider mode enable
REG_0Bh [0] USB 2.0 port polarity configuration for downstream ports 1
REG_0Bh [1] USB 2.0 port polarity configuration for downstream ports 2
REG_0Bh [2] USB 2.0 port polarity configuration for downstream ports 3
REG_0Bh [3] USB 2.0 port polarity configuration for downstream ports 4
REG_F0h [3:1] USB power switch power-on delay

8.3.4 Clock Generation

The TUSB4041I device accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is provided to the XI pin instead of a crystal, the XO pin is left open. Otherwise, if a crystal is used, the connection must follow these guidelines. Because the XI and XO pins are coupled to other leads and supplies on the PCB, keep traces as short as possible and away from any switching leads. Minimize the capacitance between the XI and XO pins by shielding C1 and C2 with the clean ground lines.

TUSB4041I TUSB4041_CLOCKGEN_SLLSEK3.gif Figure 2. TUSB4041I Clock

8.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of ±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal equivalent series resistance (ESR) of 50 Ω. If a crystal source is used, use a parallel load capacitor. The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and Specification for Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the load capacitance value.

8.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a frequency stability of ±100 PPM or better and have less than 50-ps absolute peak-to-peak jitter. Tie XI to the 1.8-V clock source, and leave XO floating.

8.3.7 Power-Up and Reset

The TUSB4041I device does not have specific power-sequencing requirements with respect to the core power (VDD) or I/O and analog power (VDD33). The core power (VDD) or I/O power (VDD33) can be powered up for an indefinite period of time while the other is not powered up if all of the following constraints are met:

  • Observe all maximum ratings and recommended operating conditions.
  • Observe all warnings about exposure to maximum rated and recommended conditions, particularly junction temperature. These apply to power transitions and normal operation.
  • Limit bus contention to 100 hours over the projected lifetime of the device while VDD33 is powered-up.
  • Do not exceed the ratings listed in the Absolute Maximum Ratings table for bus contention while VDD33 is powered-down.

A supply bus is powered-up when the voltage is within the recommended operating range. A supply bus is powered-down when it is below that range, and either stable or in transition.

The device requires a minimum reset duration of 3 ms. This reset duration is defined as the time when the power supplies are in the recommended operating range to the deassertion of the GRSTz pin. Generate the reset pulse using a programmable-delay supervisory device or using an RC circuit.

8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB4041I device supports a serial interface for configuration register access. The device can be configured by an attached I2C EEPROM or accessed as a slave by an SMBus-capable host controller. The external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the deassertion of reset. The mode, I2C master or SMBus slave, is determined by the state of SMBUSz pin at reset.

8.4.2 I2C EEPROM Operation

The TUSB4041I device supports a single-master, standard mode (100 kb/s) connection to a dedicated I2C EEPROM when the I2C interface mode is enabled. In I2C mode, the TUSB4041I device reads the contents of the EEPROM at bus address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB4041I device loads the configuration registers according to the EEPROM map. If the first byte is not 55h, the TUSB4041I device exits the I2C mode and continues execution with the default values in the configuration registers. The hub does not connect on the upstream port until the configuration is completed. If the hub detected an unprogrammed EEPROM (value other than 55h), the hub enters programming mode and a programming endpoint within the hub is enabled.

NOTE

The bytes located above offset Ah are optional. The requirement for data in those addresses is dependent on the options configured in the Device Configuration Register and Device Configuration Register 2.

For details on I2C operation, refer to the UM10204 I2C-bus Specification and User Manual.

8.4.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB4041I device supports read block and write block protocols as a slave-only SMBus device.

The TUSB4041I device slave address is 1000 1xyz, where:

  • x is the state of GANGED/SMBA2/HS_UP pin at reset
  • y is the state of FULLPWRMGMTz/SMBA1 pin at reset
  • z is the read-write (R/W) bit; 1 = read access, 0 = write access

If the TUSB4041I device is addressed by a host using an unsupported protocol, the device does not respond. The TUSB4041I device waits indefinitely for configuration by the SMBus host and does not connect on the upstream port until the SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.

For details on SMBus requirements, refer to the System Management Bus (SMBus) Specification.

NOTE

During the SMBUS configuration the hub may draw an extra current, this extra current consumption will end as soon as the CFG_ACTIVE bit is cleared. For more information refer to Hub Input Supply Current section in this datasheet.

8.5 Register Maps

8.5.1 Configuration Registers

The internal configuration registers are accessed on byte boundaries. The configuration register values are loaded with defaults, but can be overwritten when the TUSB4041I device is in I2C or SMBus mode.

Table 3. Memory Map

BYTE ADDRESS CONTENTS EEPROM CONFIGURABLE
00h ROM Signature Register No
01h Vendor ID LSB Yes
02h Vendor ID MSB Yes
03h Product ID LSB Yes
04h Product ID MSB Yes
05h Device Configuration Register Yes
06h Battery Charging Support Register Yes
07h Device Removable Configuration Register Yes
08h Port Used Configuration Register Yes
09h Reserved Yes, program to 00h
0Ah Device Configuration Register 2 Yes
0Bh USB 2.0 Port Polarity Control Register Yes
0Ch to 0Fh Reserved No
10h to 1Fh UUID Byte [15:0] No
20h to 21h LangID Byte [1:0] Yes, if customStrings is set
22h Serial Number String Length Yes, if customSerNum is set
23h Manufacturer String Length Yes, if customStrings is set
24h Product String Length Yes, if customStrings is set
25h to 2Fh Reserved No
30h to 4Fh Serial Number String Byte [31:0] Yes, if customSerNum is set
50h to 8Fh Manufacturer String Byte [63:0] Yes, if customStrings is set
90h to CFh Product String Byte [63:0] Yes, if customStrings is set
D0 to DFh Reserved No
F0h Additional Feature Configuration Register Yes
F1 to F7h Reserved No
F8h Device Status and Command Register No
F9 to FFh Reserved No

8.5.2 ROM Signature Register

Offset = 0h

Figure 3. ROM Signature Register
7 6 5 4 3 2 1 0
romSignature
RW-0

Table 4. ROM Signature Register Field Descriptions

Bit Field Type Reset Description
7:0 romSignature RW 0

ROM signature register

The TUSB4041I device uses this register in I2C mode to validate whether the attached EEPROM has been programmed. The first byte of the EEPROM is compared to the mask 55h and if not a match, the TUSB4041I device aborts the EEPROM load and executes with the register defaults.

8.5.3 Vendor ID LSB Register

Offset = 1h, reset = 51h

Figure 4. Vendor ID LSB Register
7 6 5 4 3 2 1 0
vendorIdLsb[7] vendorIdLsb[6] vendorIdLsb[5] vendorIdLsb[4] vendorIdLsb[3:1] vendorIdLsb[0]
R/RW-0 R/RW-1 R/RW-0 R/RW-1 R/RW-0 R/RW-1

Table 5. Vendor ID LSB Register Field Descriptions

Bit Field Type Reset Description
7 vendorIdLsb[7] R/RW 0

Vendor ID LSB

Least significant byte of the unique vendor ID assigned by the USB-IF; the default value of this register is 51h representing the LSB of the TI Vendor ID 0451h. The value may be overwritten to indicate a customer vendor ID.

This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-zero. If both values are non-zero, the value when reading this register will reflect the OTP ROM value.
6 vendorIdLsb[6] R/RW 1
5 vendorIdLsb[5] R/RW 0
4 vendorIdLsb[4] R/RW 1
3:1 vendorIdLsb[3:1] R/RW 0
0 vendorIdLsb[0] R/RW 1

8.5.4 Vendor ID MSB Register

Offset = 2h, reset = 04h

Figure 5. Vendor ID MSB Register
7 6 5 4 3 2 1 0
vendorIdMsb[7:3] vendorIdMsb[2] vendorIdMsb[1:0]
R/RW-0 R/RW-1 R/RW-0

Table 6. Vendor ID MSB Register Field Descriptions

Bit Field Type Reset Description
7:3 vendorIdMsb[7:3] R/RW 0

Vendor ID MSB

Most significant byte of the unique vendor ID assigned by the USB-IF; the default value of this register is 04h representing the MSB of the TI Vendor ID 0451h. The value may be overwritten to indicate a customer vendor ID.

This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-zero. If both values are non-zero, the value when reading this register shall reflect the OTP ROM value.
2 vendorIdMsb[2] R/RW 1
1:0 vendorIdMsb[1:0] R/RW 0

8.5.5 Product ID LSB Register

Offset = 3h, reset = 40h

Figure 6. Product ID LSB Register
7 6 5 4 3 2 1 0
productIdLsb[7] productIdLsb[6] productIdLsb[5:0]
R/RW-0 R/RW-1 R/RW-0

Table 7. Product ID LSB Register Field Descriptions

Bit Field Type Reset Description
7 productIdLsb[7] R/RW 0

Product ID LSB.

The default value of this register is 40h representing the LSB of the product ID assigned by TI. The value reported in the USB 2.0 device descriptor is the value of this register bit wise XORed with 00000010b. This device will always report the XORed PID LSB value of 0x42. The value may be overwritten to indicate a customer product ID.

This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-zero. If both values are non-zero, the value when reading this register will reflect the OTP ROM value.
6 productIdLsb[6] R/RW 1
5:0 productIdLsb[5:0] R/RW 0

8.5.6 Product ID MSB Register

Offset = 4h, reset = 81h

Figure 7. Product ID MSB Register
7 6 5 4 3 2 1 0
productIdMsb[7] productIdMsb[6:1] productIdMsb[0]
R/RW-1 R/RW-0 R/RW-1

Table 8. Product ID MSB Register Field Descriptions

Bit Field Type Reset Description
7 productIdMsb[7] R/RW 1

Product ID MSB

Most significant byte of the product ID assigned by TI; the default value of this register is 81h representing the MSB of the product ID assigned by TI. The value may be overwritten to indicate a customer product ID.

This field is R/W unless the OTP ROM VID and OTP ROM PID values are non-zero. If both values are non-zero, the value when reading this register will reflect the OTP ROM value.
6:1 productIdMsb[6:1] R/RW 0
0 productIdMsb[0] R/RW 1

8.5.7 Device Configuration Register

Offset = 5h

Figure 8. Device Configuration Register
7 6 5 4 3 2 1 0
customStrings customSernum RSVD RSVD ganged fullPwrMgmtz RSVD RSVD
RW-0 RW-0 RW-0 R-1 RW-X RW-X RW-0 R-0

Table 9. Device Configuration Register Field Descriptions

Bit Field Type Reset Description
7 customStrings RW 0

Custom strings enable

This bit controls the ability to write to the Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers

0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers are read only.

1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers may be loaded by EEPROM or written by SMBus.

The default value of this bit is 0.
6 customSernum RW 0

Custom serial number enable

This bit controls the ability to write to the serial number registers.

0 = The Serial Number String Length and Serial Number String registers are read only.

1 = Serial Number String Length and Serial Number String registers may be loaded by EEPROM or written by SMBus.

The default value of this bit is 0.
5 RSVD RW 0 Reserved.
4 RSVD R 1

Reserved. This bit is reserved and returns 1 when read.
3 ganged RW X

Ganged

This bit is loaded at the deassertion of reset with the value of the
GANGED/SMBA2/HS_UP pin.

0 = Each port is individually power switched and enabled by the
PWRCTL[4:1]/BATEN[4:1] pins.

1 = The power switch control for all ports is ganged and enabled by the
PWRCTL[4:1]/BATEN1 pin.

When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by an SMBus host.
2 fullPwrMgmtz RW X

Full power management

This bit is loaded at the deassertion of reset with the value of the
FULLPWRMGMTz/SMBA1 pin.

0 = Port power switching status reporting is enabled

1 = Port power switching status reporting is disabled

When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by an SMBus host.
1 RSVD RW 0

Reserved

This field is reserved and should not be altered from the default.
0 RSVD R 0

Reserved

This field is reserved and returns 0 when read.

8.5.8 Battery Charging Support Register

Offset = 6h

Figure 9. Battery Charging Support Register
7 6 5 4 3 2 1 0
RSVD batEn[3:0]
R-0 RW-X

Table 10. Battery Charging Support Register Field Descriptions

Bit Field Type Reset Description
7:4 RSVD R 0

Reserved

Read only, returns 0 when read.
3:0 batEn[3:0] RW X

Battery Charger Support. The bits in this field indicate whether the downstream port implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

Each bit corresponds directly to a downstream port, that is batEn0 corresponds to downstream port 1, and batEN1 corresponds to downstream port 2.

The default value for these bits are loaded at the deassertion of reset with the value of PWRCTL/BATEN[3:0].

When in I2C/SMBus mode the bits in this field may be overwritten by EEPROM contents or by an SMBus host.

8.5.9 Device Removable Configuration Register

Offset = 7h

Figure 10. Device Removable Configuration Register
7 6 5 4 3 2 1 0
customRmbl RSVD rmbl[3:0]
RW-0 R-0 RW-X

Table 11. Device Removable Configuration Register Field Descriptions

Bit Field Type Reset Description
7 customRmbl RW 0

Custom removable

This bit controls the ability to write to the port removable bits.

0 = rmbl[3:0] are read only, and the values are loaded from the OTP ROM.

1 = rmbl[3:0] are R/W and can be loaded by EEPROM or written by SMBus.

This bit may be written simultaneously with rmbl[3:0].
6:4 RSVD R 0

Reserved

Read only, returns 0 when read
3:0 rmbl[3:0] RW X

Removable

The bits in this field indicate whether a device attached to downstream ports 4 through 1 are removable or permanently attached.

0 = The device attached to the port is not removable.

1 = The device attached to the port is removable.

Each bit corresponds directly to a downstream port n + 1, For example: rmbl0 corresponds to downstream port 1, rmbl1 corresponds to downstream port 2, and so on.

This field is read only unless the customRmbl bit is set to 1. Otherwise, the value of this field reflects the inverted values of the OTP ROM non_rmb[3:0] field.

8.5.10 Port Used Configuration Register

Offset = 8h

Figure 11. Port Used Configuration Register
7 6 5 4 3 2 1 0
RSVD used[3:0]
R-0 RW-1

Table 12. Port Used Configuration Register Field Descriptions

Bit Field Type Reset Description
7:4 RSVD R 0

Reserved

Read only
3:0 used[3:0] RW 1

Used

The bits in this field indicate whether a port is enabled.

0 = The port is disabled.

1 = The port is enabled.

8.5.11 Device Configuration Register 2

Offset = Ah

Figure 12. Device Configuration Register 2
7 6 5 4 3 2 1 0
RSVD customBCfeatures pwrctlPol HiCurAcpModeEn cpdEN RSVD autoModeEnz RSVD
R-0 RW-0 RW-X R/RW-0 R/RW-0 RW-0 RW-X R-0

Table 13. Device Configuration Register 2 Field Descriptions

Bit Field Type Reset Description
7 RSVD R 0

Reserved

Read only, returns 0 when read.
6 customBCfeatures RW 0

Custom battery charging feature enable

This bit controls the ability to write to the battery charging feature configuration controls.

0 = The HiCurAcpModeEn and cpdEN bits are read only and the values are loaded from the OTP ROM.

1 = The HiCurAcpModeEn and cpdEN, bits are R/W and can be loaded by EEPROM or written by SMBus from this register.

This bit may be written simultaneously with HiCurAcpModeEn and cpdEN.
5 pwrctlPol RW X

Power enable polarity

This bit is loaded at the deassertion of reset with the value of the
PWRCTL_POL pin.

0 = PWRCTL polarity is active low.

1 = PWRCTL polarity is active high.

When the TUSB4041I device is in I2C mode, the TUSB4041I device loads this bit from the contents of the EEPROM.

When the TUSB4041I device is in SMBUS mode, the value may be overwritten by an SMBus host.
4 HiCurAcpModeEn R/RW 0

High-current ACP mode enable

This bit enables the high-current tablet charging mode when the automatic battery charging mode is enabled for downstream ports.

0 = High-current divider mode disabled. Legacy current divider mode enabled.

1 = High-current divider mode enabled

This bit is read only unless the customBCfeatures bit is set to 1. If customBCfeatures is 0, the value of this bit reflects the value of the
OTP ROM HiCurAcpModeEn bit.
3 cpdEN RRW 0

Enable device attach detection

This bit enables device attach detection (such as a cell-phone detect) when auto mode is enabled.

0 = Device attach detect is disabled in auto mode.

1 = Device attach detect is enabled in auto mode.

This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the OTP ROM cpdEN bit.
2 RSVD RW 0 Reserved
1 autoModeEnz RW X

Automatic mode enable(1)

This bit is loaded at the deassertion of reset with the value of the
AUTOENz/HS_SUSPEND pin.

The automatic mode only applies to downstream ports with battery charging enabled when the upstream port is not connected. Under these conditions:

0 = Automatic mode battery charging features are enabled.

1 = Automatic mode is disabled; only battery-charging DCP mode is supported.
0 RSVD R 0

Reserved

Read only, returns 0 when read.
(1) When the upstream port is connected, battery charging 1.2 CDP mode will be supported on all ports that are enabled for battery charging support regardless of the value of this bit, with the exception of port 1. CDP on port 1 is not supported when automatic mode is enabled.

8.5.12 USB 2.0 Port Polarity Control Register

Offset = Bh

Figure 13. USB 2.0 Port Polarity Control Register
7 6 5 4 3 2 1 0
customPolarity RSVD p4_usb2pol p3_usb2pol p2_usb2pol p1_usb2pol p0_usb2pol
RW-0 R-0 R/RW-0 R/RW-0 R/RW-0 R/RW-0 R/RW-0

Table 14. USB 2.0 Port Polarity Control Register Field Descriptions

Bit Field Type Reset Description
7 customPolarity RW 0

Custom USB 2.0 polarity

This bit controls the ability to write the p[4:0]_usb2pol bits.

0 = The p[4:0]_usb2pol bits are read only, and the values are loaded from the OTP ROM.

1 = The p[4:0]_usb2pol bits are R/W and can be loaded by EEPROM or written by SMBus from this register.

This bit may be written simultaneously with the p[4:0]_usb2pol bits
6:5 RSVD R 0

Reserved

Read only, returns 0 when read
4 p4_usb2pol R/RW 0

Downstream port 4 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the value of this bit reflects the value of the OTP ROM p4_usb2pol bit.
3 p3_usb2pol R/RW 0

Downstream port 3 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the value of this bit reflects the value of the OTP ROM p3_usb2pol bit.
2 p2_usb2pol R/RW 0

Downstream port 2 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the value of this bit reflects the value of the OTP ROM p2_usb2pol bit.
1 p1_usb2pol RRW 0

Downstream port 1 DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the value of this bit reflects the value of the OTP ROM p1_usb2pol bit.
0 p0_usb2pol R/RW 0

Upstream port DM/DP polarity

This bit controls the polarity of the port.

0 = USB 2.0 port polarity is as shown in the pinout.

1 = USB 2.0 port polarity is swapped from that shown in the pinout (that is, DM becomes DP, and DP becomes DM).

This bit is read only unless the customPolarity bit is set to 1. If customPolarity is 0, the value of this bit reflects the value of the OTP ROM p0_usb2pol bit.

8.5.13 UUID Byte N Register

Offset = 10h-1Fh

Figure 14. UUID Byte N Register
7 6 5 4 3 2 1 0
uuidByte[n]
R-X

Table 15. UUID Byte N Register Field Descriptions

Bit Field Type Reset Description
7:0 uuidByte[n] R X

UUID byte N

The UUID returned in the Container ID descriptor. The value of this register is provided by the device and meets the UUID requirements of the Internet Engineering Task Force (IETF) RFC 4122 A UUID URN Namespace.

8.5.14 Language ID LSB Register

Offset = 20h, reset = 09h

Figure 15. Language ID LSB Register
7 6 5 4 3 2 1 0
langIdLsb[7:4] langIdLsb[3] langIdLsb[2:1] langIdLsb[0]
R/RW-0 R/RW-1 R/RW-0 R/RW-1

Table 16. Language ID LSB Register Field Descriptions

Bit Field Type Reset Description
7:4 langIdLsb[7:4] R/RW 0

Language ID least significant byte

This register contains the value returned in the LSB of the LANGID code in string index 0. The TUSB4041I device only supports one language ID. The default value of this register is 09h representing the LSB of the LangID 0409h indicating English United States.

When the customStrings bit is set to 1, this field may be overwritten by the contents of an attached EEPROM or by an SMBus host.
3 langIdLsb[3] R/RW 1
2:1 langIdLsb[2:1] R/RW 0
0 langIdLsb[0] R/RW 1

8.5.15 Language ID MSB Register

Offset = 21h, reset = 04h

Figure 16. Language ID MSB Register
7 6 5 4 3 2 1 0
langIdMsb[7:3] langIdMsb[2] langIdMsb[1:0]
R/RW-0 R/RW-1 R/RW-0

Table 17. Language ID MSB Register Field Descriptions

Bit Field Type Reset Description
7:3 langIdMsb[7:3] R/RW 0

Language ID most significant byte

This register contains the value returned in the MSB of the LANGID code in string index 0. The TUSB4041I device only supports one language ID. The default value of this register is 04h representing the MSB of the LangID 0409h indicating English United States.

When the customStrings bit is set to 1, this field may be overwritten by the contents of an attached EEPROM or by an SMBus host.
2 langIdMsb[2] R/RW 1
1:0 langIdMsb[1:0] R/RW 0

8.5.16 Serial Number String Length Register

Offset = 22h

Figure 17. Serial Number String Length Register
7 6 5 4 3 2 1 0
RSVD serNumStringLen[5] serNumStringLen[4:3] serNumStringLen[2:0]
R-0 R/RW-0 R/RW-1 R/RW-0

Table 18. Serial Number String Length Register Field Descriptions

Bit Field Type Reset Description
7:6 RSVD R 0

Reserved

Read only, returns 0 when read.
5 serNumStringLen[5] R/RW 0

Serial number string length

The string length in bytes for the serial number string. The default value is 18h indicating that a 24-byte serial number string is supported. The maximum string length is 32 bytes.

When the customSernum bit is set to 1, this field may be overwritten by the contents of an attached EEPROM or by an SMBus host.

When the field is non-zero, a serial number string of serNumbStringLen bytes is returned at string index 1 from the data contained in the Serial Number String registers.
4:3 serNumStringLen[4:3] R/RW 1
2:0 serNumStringLen[2:0] R/RW 0

8.5.17 Manufacturer String Length Register

Offset = 23h

Figure 18. Manufacturer String Length Register
7 6 5 4 3 2 1 0
RSVD mfgStringLen
R-0 R/RW-0

Table 19. Manufacturer String Length Register Field Descriptions

Bit Field Type Reset Description
7 RSVD R 0

Reserved

Read only, returns 0 when read
6:0 mfgStringLen R/RW 0

Manufacturer string length

The string length in bytes for the manufacturer string. The default value is 0, indicating that a manufacturer string is not provided. The maximum string length is 64 bytes.

When the customStrings bit is set to 1, this field may be overwritten by the contents of an attached EEPROM or by an SMBus host.

When the field is non-zero, a manufacturer string of mfgStringLen bytes is returned at string index 3 from the data contained in the Manufacturer String registers.

8.5.18 Product String Length Register

Offset = 24h

Figure 19. Product String Length Register
7 6 5 4 3 2 1 0
RSVD prodStringLen
R-0 R/RW-0

Table 20. Product String Length Register Field Descriptions

Bit Field Type Reset Description
7 RSVD R 0

Reserved

Read only, returns 0 when read.
6:0 prodStringLen R/RW 0

Product string length

The string length in bytes for the product string. The default value is 0, indicating that a product string is not provided. The maximum string length is 64 bytes.

When the customStrings bit is set to 1, this field may be overwritten by the contents of an attached EEPROM or by an SMBus host.

When the field is non-zero, a product string of prodStringLen bytes is returned at string index 3 from the data contained in the Product String registers.

8.5.19 Serial Number String Registers

Offset = 30h-4Fh

Figure 20. Serial Number String Registers
7 6 5 4 3 2 1 0
serialNumber[n]
R/RW-X

Table 21. Serial Number String Registers Field Descriptions

Bit Field Type Reset Description
7:0 serialNumber[n] R/RW X

Serial Number byte N

The serial number returned in the Serial Number string descriptor at string index 1. The default value of these registers is assigned by TI. When customSernum is 1, these registers may be overwritten by EEPROM contents or by an SMBus host.

8.5.20 Manufacturer String Registers

Offset = 50h-8Fh

Figure 21. Manufacturer String Registers
7 6 5 4 3 2 1 0
mfgStringByte[n]
R/W-0

Table 22. Manufacturer String Registers Field Descriptions

Bit Field Type Reset Description
7:0 mfgStringByte[n] R/W 0

Manufacturer string byte N

These registers provide the string values returned for string index 3 when mfgStringLen is greater than 0. The number of bytes returned in the string is equal to mfgStringLen.

The programmed data should be in UNICODE UTF-16LE encodings as defined by the Unicode Standard, Worldwide Character Encoding, Version 5.0.

8.5.21 Product String Byte N Register

Offset = 90h-CFh

Figure 22. Product String Byte N Register
7 6 5 4 3 2 1 0
prodStringByte[n]
R/RW-0

Table 23. Product String Byte N Register Field Descriptions

Bit Field Type Reset Description
7:0 prodStringByte[n] R/RW 0

Product string byte N

These registers provide the string values returned for string index 2 when prodStringLen is greater than 0. The number of bytes returned in the string is equal to prodStringLen.

The programmed data should be in UNICODE UTF-16LE encodings as defined by the Unicode Standard, Worldwide Character Encoding, Version 5.0.

8.5.22 Additional Feature Configuration Register

Offset = F0h

Figure 23. Additional Feature Configuration Register
7 6 5 4 3 2 1 0
RSVD stsOutputEn pwronTime RSVD
R-0 R/RW-0 R/W-0 R/W-0

Table 24. Additional Feature Configuration Register Field Descriptions

Bit Field Type Reset Description
7:5 RSVD R 0

Reserved

Read only, returns 0 when read.
4 RSVD R/RW 0 Reserved.
3:1 pwronTime RW 0

Power-on delay time

When OTP ROM pwronTime field is all 0, this field sets the delay time from the removal disable of PWRCTL to the enable of PWRCTL when transitioning battery charging modes. For example, when disabling the power on a transition from a custom charging mode to dedicated charging port mode. The nominal timing is defined as follows:

Equation 1. TPWRON_EN = (pwronTime + 1) x 200 ms

This field may be overwritten by EEPROM contents or by an SMBus host.
0 RSVD RW 0 Reserved

8.5.23 Device Status and Command Register

Offset = F8h

Figure 24. Device Status and Command Register
7 6 5 4 3 2 1 0
RSVD smbusRst cfgActive
R-0 W1S-0 W1C-0

Table 25. Device Status and Command Register Field Descriptions

Bit Field Type Reset Description
7:2 RSVD R 0

Reserved

Read only, returns 0 when read
1 smbusRst W1S 0

SMBus interface reset

This bit loads the registers back to their GRSTz values.

This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect.
0 cfgActive W1C 0

Configuration active

This bit indicates that configuration of the TUSB4041I device is currently active. The bit is set by hardware when the device enters the I2C or SMBus mode. The TUSB4041I device does not connect on the upstream port while this bit is 1.

When in the SMBus mode, this bit must be cleared by the SMBus host to exit the configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.