SLLSEK3E July   2015  – September 2017 TUSB4041I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Byte N Register
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 Downstream Port 3 Implementation
        5. 9.2.2.5 Downstream Port 4 Implementation
        6. 9.2.2.6 VBUS Power Switch Implementation
        7. 9.2.2.7 Clock, Reset, and Miscellaneous
        8. 9.2.2.8 TUSB4041I Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB4041I Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 TUSB4041I Power Supply

The user should implement VDD as a single power plane, as well as VDD33.

  • The VDD pins of the TUSB4041I supply 1.1-V (nominal) power to the core of the TUSB4041I device. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device because of the high current draw on the power rail. The user may need to adjust the output of the core voltage regulator to account for this, or select a ferrite bead with low DC resistance (less than 0.05 Ω).
  • The VDD33 pins of the TUSB4041I device supply 3.3-V power rail to the I/O of the TUSB4041I device. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk capacitors can be placed anywhere on the power rail. Place the smaller decoupling capacitors as close to the TUSB4041I power pins as possible with an optimal grouping of two capacitors of differing values per pin.

10.2 Downstream Port Power

  • A source capable of supplying 5 V and up to 500 mA per port must supply the downstream port power, VBUS. The TUSB4041I signals can control the downstream port power switches. Leaving the downstream port power as always enabled is also possible.
  • The VBUS of each downstream port requires a large-bulk low-ESR capacitor of 22 µF or larger to limit in-rush current.
  • TI recommends the ferrite beads on the VBUS pins of the downstream USB port connections for both ESD and EMI reasons. A 0.1-µF capacitor on the USB connector side of the ferrite provides a low-impedance path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground

TI recommends to use only one board ground plane in the design which provides the best image plane for signal traces running above the plane. Connect the thermal pad of the TUSB4041I and any of the voltage regulators to this plane with vias. An earth or chassis ground is implemented only near the USB port connectors on a different plane for EMI and ESD purposes.