SLLSEZ0E April 2017 – April 2018 TUSB544
PRODUCTION DATA.
The TUSB544 is in GPIO configuration when I2C_EN = “0” or "F". The TUSB544 supports operational combinations with USB and two different Type-C Alternate Modes.. One combination includes USB and Alternate Mode DisplayPort, and the other combination includes USB and custom Alternate Mode. For each operational combination the data path directions can be further set using the DIR[1:0] pins or through I2C to enable the device to operate in the source or sink sides. Please refer to Table 2 for all the configuration of all the operational modes.
When the device is set to operate in a USB and Alternate Mode DisplayPort the following configurations can be further set: USB3.1 only, 2 DisplayPort lanes + USB3.1, or 4 DisplayPort lanes (no USB3.1). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB3.1 only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXP/N to SBU1/2 mapping is controlled based on Table 3..
When the device is set to operate in a USB and custom Alternate Mode the following configurations can be further set: USB3.1 only, 2 Channels of custom Alternate Mode + USB3.1, or 4 Channels of custom Alternate Mode (no USB3.1). The CTL1 pin controls whether custom Alternate Mode is enabled. The combination of CTL1 and CTL0 selects between USB3.1 only, 2 channels of custom Alternate Mode, or 4 channels of custom Alternate Mode as detailed in Table 2. The AUXP/N to SBU1/2 mapping is controlled based on Table 3.
Further data path direction control can be achieved using the SWAP pin. When set high, the SWAP pin reverses the data path direction on all the channels and swaps the equalization settings of the upstream and downstream facing input ports. This pin may be found useful in active cable application with TUSB544 installed on only one end. The SWAP pin can be set based on which cable end is plugged to the source or sink side receptacle
After power-up (VCC from 0 V to 3.3 V), the TUSB544 will default to USB3.1 mode. The USB PD controller, upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device, must take TUSB544 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
DIR1
PIN |
DIR0
PIN |
CTL1
PIN |
CTL0
PIN |
FLIP
PIN |
TUSB544 CONFIGURATION | VESA DisplayPort ALT MODE
DFP_D Configuration |
---|---|---|---|---|---|---|
USB + DisplayPort Alternate Mode (Source Side) | ||||||
L | L | L | L | L | Power Down | — |
L | L | L | L | H | Power Down | — |
L | L | L | H | L | One Port USB 3.1 - No Flip | — |
L | L | L | H | H | One Port USB 3.1 – With Flip | — |
L | L | H | L | L | 4 Lane DP - No Flip | C and E |
L | L | H | L | H | 4 Lane DP – with Flip | C and E |
L | L | H | H | L | One Port USB 3.1 + 2 Lane DP- No Flip | D and F |
L | L | H | H | H | One Port USB 3.1 + 2 Lane DP– with Flip | D and F |
USB + DisplayPort Alternate Mode (Sink Side) | ||||||
L | H | L | L | L | Power Down | – |
L | H | L | L | H | Power Down | – |
L | H | L | H | L | One Port USB 3.1 - No Flip | – |
L | H | L | H | H | One Port USB 3.1 – With Flip | – |
L | H | H | L | L | 4 Lane DP - No Flip | C and E |
L | H | H | L | H | 4 Lane DP – With Flip | C and E |
L | H | H | H | L | One Port USB 3.1 + 2 Lane DP- No Flip | D and F |
L | H | H | H | H | One Port USB 3.1 + 2 Lane DP– With Flip | D and F |
USB + Custom Alternate Mode (Source Side) | ||||||
H | L | L | L | L | Power Down | – |
H | L | L | L | H | Power Down | – |
H | L | L | H | L | One Port USB 3.1 - No Flip | – |
H | L | L | H | H | One Port USB 3.1 – With Flip | – |
H | L | H | L | L | 4 Channel Custom Alt Mode - No Flip | – |
H | L | H | L | H | 4 Channel Custom Alt Mode– With Flip | – |
H | L | H | H | L | One Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip |
– |
H | L | H | H | H | One Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip |
– |
USB + Custom Alternate Mode (Sink Side) | ||||||
H | H | L | L | L | Power Down | - |
H | H | L | L | H | Power Down | - |
H | H | L | H | L | One Port USB 3.1 - No Flip | - |
H | H | L | H | H | One Port USB 3.1 – With Flip | - |
H | H | H | L | L | 4 Channel Custom Alt Mode - No Flip | - |
H | H | H | L | H | 4 Channel Custom Alt Mode– With Flip | - |
H | H | H | H | L | One Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip |
- |
H | H | H | H | H | One Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip |
- |
CTL1 pin | FLIP pin | Mapping |
---|---|---|
H | L | AUXP -> SBU1
AUXN -> SBU2 |
H | H | AUXP -> SBU2
AUXN -> SBU1 |
L > 2ms | X | Open |
details the TUSB544 mux routing. This table is valid for GPIO mode. This table is also valid for I2C mode for the case where CH_SWAP_SEL = 4'b0000 or 4'b1111.
SWAP = L | SWAP = H | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
From | From | To | From | From | To | |||||
DIR1
PIN |
DIR0
PIN |
CTL1
PIN |
CTL0
PIN |
FLIP
PIN |
Rx EQ Control
PINS |
Input
PIN |
Output
PIN |
Rx EQ Control
PINS |
Input
PIN |
Output
PIN |
USB + DisplayPort Alternate Mode (Source Side) | ||||||||||
L | L | L | L | L | NA | NA | NA | NA | NA | NA |
L | L | L | L | H | NA | NA | NA | NA | NA | NA |
L | L | L | H | L | DEQ[1:0] | DRX1P | URX1P (SSRXP) | DEQ[1:0] | URX1P (SSTXP) | DRX1P |
DEQ[1:0] | DRX1N | URX1N (SSRXN) | DEQ[1:0] | URX1N (SSTXN) | DRX1N | |||||
UEQ[1:0] | UTX1P (SSTXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (SSRXP) | |||||
UEQ[1:0] | UTX1N (SSTXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (SSRXN) | |||||
L | L | L | H | H | DEQ[1:0] | DRX2P | URX2P (SSRXP) | DEQ[1:0] | URX2P (SSTXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (SSRXN) | DEQ[1:0] | URX2N (SSTXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (SSTXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (SSRXP) | |||||
UEQ[1:0] | UTX2N (SSTXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (SSRXN) | |||||
L | L | H | L | L | UEQ[1:0] | URX2P (DP0P) | DRX2P | UEQ[1:0] | DRX2P | URX2P (DP0P) |
UEQ[1:0] | URX2N (DP0N) | DRX2N | UEQ[1:0] | DRX2N | URX2N (DP0N) | |||||
UEQ[1:0] | UTX2P (DP1P) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (DP1P) | |||||
UEQ[1:0] | UTX2N (DP1N) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (DP1N) | |||||
UEQ[1:0] | UTX1P (DP2P) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (DP2P) | |||||
UEQ[1:0] | UTX1N (DP2N) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (DP2N) | |||||
UEQ[1:0] | URX1P (DP3P) | DRX1P | UEQ[1:0] | DRX1P | URX1P (DP3P) | |||||
UEQ[1:0] | URX1N (DP3N) | DRX1N | UEQ[1:0] | DRX1N | URX1N (DP3N) | |||||
L | L | H | L | H | UEQ[1:0] | URX1P (DP0P) | DRX1P | UEQ[1:0] | DRX1P | URX1P (DP0P) |
UEQ[1:0] | URX1N (DP0N) | DRX1N | UEQ[1:0] | DRX1N | URX1N (DP0N) | |||||
UEQ[1:0] | UTX1P (DP1P) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (DP1P) | |||||
UEQ[1:0] | UTX1N (DP1N) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (DP1N) | |||||
UEQ[1:0] | UTX2P (DP2P) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (DP2P) | |||||
UEQ[1:0] | UTX2N (DP2N) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (DP2N) | |||||
UEQ[1:0] | URX2P (DP3P) | DRX2P | UEQ[1:0] | DRX2P | URX2P (DP3P) | |||||
UEQ[1:0] | URX2N (DP3N) | DRX2N | UEQ[1:0] | DRX2N | URX2N (DP3N) | |||||
L | L | H | H | L | DEQ[1:0] | DRX1P | URX1P (SSRXP) | DEQ[1:0] | URX1P (SSTXP) | DRX1P |
DEQ[1:0] | DRX1N | URX1N (SSRXN) | DEQ[1:0] | URX1N (SSTXN) | DRX1N | |||||
UEQ[1:0] | UTX1P (SSTXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (SSRXP) | |||||
UEQ[1:0] | UTX1N (SSTXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (SSRXN) | |||||
UEQ[1:0] | URX2P (DP0P) | DRX2P | UEQ[1:0] | DRX2P | URX2P (DP0P) | |||||
UEQ[1:0] | URX2N (DP0N) | DRX2N | UEQ[1:0] | DRX2N | URX2N (DP0N) | |||||
UEQ[1:0] | UTX2P (DP1P) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (DP1P) | |||||
UEQ[1:0] | UTX2N (DP1N) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (DP1N) | |||||
L | L | H | H | H | DEQ[1:0] | DRX2P | URX2P (SSRXP) | DEQ[1:0] | URX2P (SSTXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (SSRXN) | DEQ[1:0] | URX2N (SSTXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (SSTXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (SSRXP) | |||||
UEQ[1:0] | UTX2N (SSTXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (SSRXN) | |||||
UEQ[1:0] | URX1P (DP0P) | DRX1P | UEQ[1:0] | DRX1P | URX1P (DP0P) | |||||
UEQ[1:0] | URX1N (DP0N) | DRX1N | UEQ[1:0] | DRX1N | URX1N (DP0N) | |||||
UEQ[1:0] | UTX1P (DP1P) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (DP1P) | |||||
UEQ[1:0] | UTX1N (DP1N) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (DP1N) | |||||
USB + DisplayPort Alternate Mode (Sink Side) | ||||||||||
L | H | L | L | L | NA | NA | NA | NA | NA | NA |
L | H | L | L | H | NA | NA | NA | NA | NA | NA |
L | H | L | H | L | UEQ[1:0] | UTX2P | DTX2P (SSRXP) | UEQ[1:0] | DTX2P (SSTXP) | UTX2P |
UEQ[1:0] | UTX2N | DTX2N (SSRXN) | UEQ[1:0] | DTX2N (SSTXN) | UTX2N | |||||
DEQ[1:0] | DRX2P (SSTXP) | URX2P | DEQ[1:0] | URX2P | DRX2P (SSRXP) | |||||
DEQ[1:0] | DRX2N (SSTXN) | URX2N | DEQ[1:0] | URX2N | DRX2N (SSRXN) | |||||
L | H | L | H | H | UEQ[1:0] | UTX1P | DTX1P (SSRXP) | UEQ[1:0] | DTX1P (SSTXP) | UTX1P |
UEQ[1:0] | UTX1N | DTX1N (SSRXN) | UEQ[1:0] | DTX1N (SSTXN) | UTX1N | |||||
DEQ[1:0] | DRX1P (SSTXP) | URX1P | DEQ[1:0] | URX1P | DRX1P (SSRXP) | |||||
DEQ[1:0] | DRX1N (SSTXN) | URX1N | DEQ[1:0] | URX1N | DRX1N (SSRXN) | |||||
L | H | H | L | L | UEQ[1:0] | URX2P | DRX2P (DP3P) | UEQ[1:0] | DRX2P (DP3P) | URX2P |
UEQ[1:0] | URX2N | DRX2N (DP3N) | UEQ[1:0] | DRX2N (DP3N) | URX2N | |||||
UEQ[1:0] | UTX2P | DTX2P (DP2P) | UEQ[1:0] | DTX2P (DP2P) | UTX2P | |||||
UEQ[1:0] | UTX2N | DTX2N (DP2N) | UEQ[1:0] | DTX2N (DP2N) | UTX2N | |||||
UEQ[1:0] | UTX1P | DTX1P (DP1P) | UEQ[1:0] | DTX1P (DP1P) | UTX1P | |||||
UEQ[1:0] | UTX1N | DTX1N (DP1N) | UEQ[1:0] | DTX1N (DP1N) | UTX1N | |||||
UEQ[1:0] | URX1P | DRX1P (DP0P) | UEQ[1:0] | DRX1P (DP0P) | URX1P | |||||
UEQ[1:0] | URX1P | DRX1N (DP0P) | UEQ[1:0] | DRX1N (DP0N) | URX1N | |||||
L | H | H | L | H | UEQ[1:0] | URX1P | DRX1P (DP3P) | UEQ[1:0] | DRX1P (DP3P) | URX1P |
UEQ[1:0] | URX1N | DRX1N (DP3N) | UEQ[1:0] | DRX1N (DP3N) | URX1N | |||||
UEQ[1:0] | UTX1P | DTX1P (DP2P) | UEQ[1:0] | DTX1P (DP2P) | UTX1P | |||||
UEQ[1:0] | UTX1N | DTX1N (DP2N) | UEQ[1:0] | DTX1N (DP2N) | UTX1N | |||||
UEQ[1:0] | UTX2P | DTX2P (DP1P) | UEQ[1:0] | DTX2P (DP1P) | UTX2P | |||||
UEQ[1:0] | UTX2N | DTX2N (DP1N) | UEQ[1:0] | DTX2N (DP1N) | UTX2N | |||||
UEQ[1:0] | URX2P | DRX2P (DP0P) | UEQ[1:0] | DRX2P (DP0P) | URX2P | |||||
UEQ[1:0] | URX2N | DRX2N (DP0N) | UEQ[1:0] | DRX2N (DP0N) | URX2N | |||||
L | H | H | H | L | DEQ[1:0] | DRX2P (SSRXP) | URX2P | DEQ[1:0] | URX2P | DRX2P (SSRXP) |
DEQ[1:0] | DRX2N (SSRXN) | URX2N | DEQ[1:0] | URX2N | DRX2N (SSRXN) | |||||
UEQ[1:0] | UTX2P | DTX2P (SSTXP) | UEQ[1:0] | DTX2P (SSTXP) | UTX2P | |||||
UEQ[1:0] | UTX2N | DTX2N (SSTXN) | UEQ[1:0] | DTX2N (SSTXN) | UTX2N | |||||
UEQ[1:0] | URX1P | DRX1P (DP0P) | UEQ[1:0] | DRX1P (DP0P) | URX1P | |||||
UEQ[1:0] | URX1N | DRX1N (DP0N) | UEQ[1:0] | DRX1N (DP0N) | URX1N | |||||
UEQ[1:0] | UTX1P | DTX1P (DP1P) | UEQ[1:0] | DTX1P (DP1P) | UTX1P | |||||
UEQ[1:0] | UTX1N | DTX1N (DP1N) | UEQ[1:0] | DTX1N (DP1N) | UTX1N | |||||
L | H | H | H | H | DEQ[1:0] | DRX1P (SSRXP) | URX1P | DEQ[1:0] | URX1P | DRX1P (SSRXP) |
DEQ[1:0] | DRX1N (SSRXN) | URX1N | DEQ[1:0] | URX1N | DRX1N (SSRXN) | |||||
UEQ[1:0] | UTX1P | DTX1P (SSTXP) | UEQ[1:0] | DTX1P (SSTXP) | UTX1P | |||||
UEQ[1:0] | UTX1N | DTX1N (SSTXN) | UEQ[1:0] | DTX1N (SSTXN) | UTX1N | |||||
UEQ[1:0] | URX2P | DRX2P (DP0P) | UEQ[1:0] | DRX2P (DP0P) | URX2P | |||||
UEQ[1:0] | URX2N | DRX2N (DP0N) | UEQ[1:0] | DRX2N (DP0N) | URX2N | |||||
UEQ[1:0] | UTX2P | DTX2P (DP1P) | UEQ[1:0] | DTX2P (DP1P) | UTX2P | |||||
UEQ[1:0] | UTX2N | DTX2N (DP1N) | UEQ[1:0] | DTX2N (DP1N) | UTX2N | |||||
USB + Custom Alternate Mode (Source Side) | ||||||||||
H | L | L | L | L | NA | NA | NA | NA | NA | NA |
H | L | L | L | H | NA | NA | NA | NA | NA | NA |
H | L | L | H | L | DEQ[1:0] | DRX1P | URX1P (SSRXP) | DEQ[1:0] | URX1P (SSTXP) | DRX1P |
DEQ[1:0] | DRX1N | URX1N (SSRXN) | DEQ[1:0] | URX1N (SSTXN) | DRX1N | |||||
UEQ[1:0] | UTX1P (SSTXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (SSRXP) | |||||
UEQ[1:0] | UTX1N (SSTXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (SSRXN) | |||||
H | L | L | H | H | DEQ[1:0] | DRX2P | URX2P (SSRXP) | DEQ[1:0] | URX2P (SSTXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (SSRXN) | DEQ[1:0] | URX2N (SSTXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (SSTXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (SSRXP) | |||||
UEQ[1:0] | UTX2N (SSTXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (SSRXN) | |||||
H | L | H | L | L | DEQ[1:0] | DRX2P | URX2P (LN1RXP) | DEQ[1:0] | URX2P (LN1RXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (LN1RXN) | DEQ[1:0] | URX2N (LN1RXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (LN1TXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (LN1TXP) | |||||
UEQ[1:0] | UTX2N (LN1TXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (LN1TXN) | |||||
UEQ[1:0] | UTX1P (LN0TXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (LN0TXP) | |||||
UEQ[1:0] | UTX1N (LN0TXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (LN0TXN) | |||||
DEQ[1:0] | DRX1P | URX1P (LN0RXP) | DEQ[1:0] | URX1P (LN0RXP) | DRX1P | |||||
DEQ[1:0] | DRX1N | URX1N (LN0RXN) | DEQ[1:0] | URX1N (LN0RXN) | DRX1N | |||||
H | L | H | L | H | DEQ[1:0] | DRX1P | URX1P (LN1RXP) | DEQ[1:0] | URX1P (LN1RXP) | DRX1P |
DEQ[1:0] | DRX1N | URX1N (LN1RXN) | DEQ[1:0] | URX1N (LN1RXN) | DRX1N | |||||
UEQ[1:0] | UTX1P (LN1TXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (LN1TXP) | |||||
UEQ[1:0] | UTX1N (LN1TXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (LN1TXN) | |||||
UEQ[1:0] | UTX2P (LN0TXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (LN0TXP) | |||||
UEQ[1:0] | UTX2N (LN0TXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (LN0TXN) | |||||
H | L | H | H | L | DEQ[1:0] | DRX2P | URX2P (LN0RXP) | DEQ[1:0] | URX2P (LN0RXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (LN0RXN) | DEQ[1:0] | URX2N (LN0RXN) | DRX2N | |||||
DEQ[1:0] | DRX1P | URX1P (SSRXP) | DEQ[1:0] | URX1P (SSTXP) | DRX1P | |||||
DEQ[1:0] | DRX1N | URX1N (SSRXN) | DEQ[1:0] | URX1N (SSTXN) | DRX1N | |||||
UEQ[1:0] | UTX1P (SSTXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (SSRXP) | |||||
UEQ[1:0] | UTX1N (SSTXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (SSRXN) | |||||
UEQ[1:0] | UTX2P (LN0TXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (LN0TXP) | |||||
UEQ[1:0] | UTX2N (LN0TXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (LN0TXN) | |||||
DEQ[1:0] | DRX2P | URX2P (LN0RXP) | DEQ[1:0] | URX2P (LN0RXP) | DRX2P | |||||
DEQ[1:0] | DRX2N | URX2N (LN0RXN) | DEQ[1:0] | URX2N (LN0RXN) | DRX2N | |||||
H | L | H | H | H | DEQ[1:0] | DRX2P | URX2P (SSRXP) | DEQ[1:0] | URX2P (SSTXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (SSRXN) | DEQ[1:0] | URX2N (SSTXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (SSTXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (SSRXP) | |||||
UEQ[1:0] | UTX2N (SSTXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (SSRXN) | |||||
UEQ[1:0] | UTX1P (LN0TXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (LN0TXP) | |||||
UEQ[1:0] | UTX1N (LN0TXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (LN0TXN) | |||||
DEQ[1:0] | DRX1P | URX1P (LN0RXP) | DEQ[1:0] | URX1P (LN0RXP) | DRX1P | |||||
DEQ[1:0] | DRX1N | URX1N (LN0RXN) | DEQ[1:0] | URX1N (LN0RXN) | DRX1N | |||||
USB + Custom Alternate Mode (Sink Side) | ||||||||||
H | H | L | L | L | NA | NA | NA | NA | NA | NA |
H | H | L | L | H | NA | NA | NA | NA | NA | NA |
H | H | L | H | L | UEQ[1:0] | UTX2P | DTX2P (SSRXP) | UEQ[1:0] | DTX2P (SSTXP) | UTX2P |
UEQ[1:0] | UTX2N | DTX2N (SSRXN) | UEQ[1:0] | DTX2N (SSTXN) | UTX2N | |||||
DEQ[1:0] | DRX2P (SSTXP) | URX2P | DEQ[1:0] | URX2P | DRX2P (SSRXP) | |||||
DEQ[1:0] | DRX2N (SSTXN) | URX2N | DEQ[1:0] | URX2N | DRX2N (SSRXN) | |||||
H | H | L | H | H | UEQ[1:0] | UTX1P | DTX1P (SSRXP) | UEQ[1:0] | DTX1P (SSTXP) | UTX1P |
UEQ[1:0] | UTX1N | DTX1N (SSRXN) | UEQ[1:0] | DTX1N (SSTXN) | UTX1N | |||||
DEQ[1:0] | DRX1P (SSTXP) | URX1P | DEQ[1:0] | URX1P | DRX1P (SSRXP) | |||||
DEQ[1:0] | DRX1N (SSTXN) | URX1N | DEQ[1:0] | URX1N | DRX1N (SSRXN) | |||||
H | H | H | L | L | DEQ[1:0] | DRX2P | URX2P (LN1TXP) | DEQ[1:0] | URX2P (LN1TXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (LN1TXN) | DEQ[1:0] | URX2N (LN1TXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (LN1RXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (LN1RXP) | |||||
UEQ[1:0] | UTX2N (LN1RXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (LN1RXN) | |||||
UEQ[1:0] | UTX1P (LN0RXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (LN0RXP) | |||||
UEQ[1:0] | UTX1N (LN0RXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (LN0RXN) | |||||
DEQ[1:0] | DRX1P | URX1P (LN0RXP) | DEQ[1:0] | URX1P (LN0RXP) | DRX1P | |||||
DEQ[1:0] | DRX1N | URX1N (LN0RXN) | DEQ[1:0] | URX1N (LN0RXN) | DRX1N | |||||
H | H | H | L | H | DEQ[1:0] | DRX2P | URX2P (LN0RXP) | DEQ[1:0] | URX2P (LN0RXP) | DRX2P |
DEQ[1:0] | DRX2N | URX2N (LN0RXN) | DEQ[1:0] | URX2N (LN0RXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (LN0RXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (LN0RXP) | |||||
UEQ[1:0] | UTX2N (LN0RXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (LN0RXN) | |||||
UEQ[1:0] | UTX1P (LN0RXP) | DTX1P | UEQ[1:0] | DTX1P | UTX1P (LN0RXP) | |||||
UEQ[1:0] | UTX1N (LN0RXN) | DTX1N | UEQ[1:0] | DTX1N | UTX1N (LN0RXN) | |||||
DEQ[1:0] | DRX1P | URX1P (LN0TXP) | DEQ[1:0] | URX1P (LN0TXP) | DRX1P | |||||
DEQ[1:0] | DRX1N | URX1N (LN0TXN) | DEQ[1:0] | URX1N (LN0TXN) | DRX1N | |||||
H | H | H | H | L | UEQ[1:0] | UTX2P | DTX2P (SSRXP) | UEQ[1:0] | DTX2P (SSTXP) | UTX2P |
UEQ[1:0] | UTX2N | DTX2N (SSRXN) | UEQ[1:0] | DTX2N (SSTXN) | UTX2N | |||||
DEQ[1:0] | DRX2P (SSTXP) | URX2P | DEQ[1:0] | URX2P | DRX2P (SSRXP) | |||||
DEQ[1:0] | DRX2N (SSTXN) | URX2N | DEQ[1:0] | URX2N | DRX2N (SSRXN) | |||||
UEQ[1:0] | UTX1P | DTX1P (LN0RXP) | UEQ[1:0] | DTX1P (LN0RXP) | UTX1P | |||||
UEQ[1:0] | UTX1N | DTX1N(LN0RXN) | UEQ[1:0] | DTX1N(LN0RXN) | UTX1N | |||||
DEQ[1:0] | DRX1P (LN0TXP) | URX1P | DEQ[1:0] | URX1P | DRX1P (LN0TXP) | |||||
DEQ[1:0] | DRX1N (LN0TXN) | URX1N | DEQ[1:0] | URX1N | DRX1N (LN0TXN) | |||||
H | H | H | H | H | UEQ[1:0] | UTX1P | DTX1P (SSRXP) | UEQ[1:0] | DTX1P (SSSXP) | UTX1P |
UEQ[1:0] | UTX1N | DTX1N (SSRXN) | UEQ[1:0] | DTX1N (SSSXN) | UTX1N | |||||
DEQ[1:0] | DRX1P (SSTXP) | URX1P | DEQ[1:0] | URX1P | DRX1P (SSRXP) | |||||
DEQ[1:0] | DRX1N (SSTXN) | URX1N | DEQ[1:0] | URX1N | DRX1N (SSRXN) | |||||
DEQ[1:0] | DRX2P | URX2P (LN0TXP) | DEQ[1:0] | URX2P (LN0TXP) | DRX2P | |||||
DEQ[1:0] | DRX2N | URX2N (LN0TXN) | DEQ[1:0] | URX2N (LN0TXN) | DRX2N | |||||
UEQ[1:0] | UTX2P (LN0RXP) | DTX2P | UEQ[1:0] | DTX2P | UTX2P (LN0RXP) | |||||
UEQ[1:0] | UTX2N (LN0RXN) | DTX2N | UEQ[1:0] | DTX2N | UTX2N (LN0RXN) |