SLLSEZ0E April   2017  – April 2018 TUSB544

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 modes
      8. 7.4.8 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 The Following Procedure Should be Followed to Write to TUSB544 I2C Registers:
      2. 7.5.2 The Following Procedure Should be Followed to Read the TUSB544 I2C Registers:
      3. 7.5.3 The Following Procedure Should be Followed for Setting a Starting Sub-Address for I2C Reads:
    6. 7.6 Register Maps
      1. 7.6.1 TUSB544 Registers
        1. 7.6.1.1  GENERAL_4 Register (Offset = Ah) [reset = 1h]
          1. Table 13. GENERAL_4 Register Field Descriptions
        2. 7.6.1.2  GENERAL_5 Register (Offset = Bh) [reset = 0h]
          1. Table 14. GENERAL_5 Register Field Descriptions
        3. 7.6.1.3  GENERAL_6 Register (Offset = Ch) [reset = 0h]
          1. Table 15. GENERAL_6 Register Field Descriptions
        4. 7.6.1.4  DISPLAYPORT_1 Register (Offset = 10h) [reset = 0h]
          1. Table 16. DISPLAYPORT Register Field Descriptions
        5. 7.6.1.5  DISPLAYPORT_2 Register (Offset = 11h) [reset = 0h]
          1. Table 17. DISPLAYPORT_2 Register Field Descriptions
        6. 7.6.1.6  DISPLAYPORT_3 Register (Offset = 12h) [reset = 0h]
          1. Table 18. DISPLAYPORT_3 Register Field Descriptions
        7. 7.6.1.7  DISPLAYPORT_4 Register (Offset = 13h) [reset = 0h]
          1. Table 19. DISPLAYPORT_4 Register Field Descriptions
        8. 7.6.1.8  DISPLAYPORT_5 Register (Offset = 1Bh) [reset = 0h]
          1. Table 20. DISPLAYPORT_5 Register Field Descriptions
        9. 7.6.1.9  USB3.1_1 Register (Offset = 20h) [reset = 0h]
          1. Table 21. USB3.1 Register Field Descriptions
        10. 7.6.1.10 USB3.1_2 Register (Offset = 21h) [reset = 0h]
          1. Table 22. USB3.1_2 Register Field Descriptions
        11. 7.6.1.11 USB3.1_3 Register (Offset = 22h) [reset = 0h]
          1. Table 23. USB3.1_3 Register Field Descriptions
        12. 7.6.1.12 USB3.1_4 Register (Offset = 23h) [reset = 23h]
          1. Table 24. USB3.1_4 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 8.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
      4. 8.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 8.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 8.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 8.3.7 USB3.1 and 4 Lane of Custom Alt Mode
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.7 USB3.1 modes

The TUSB544 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB 3.1 interface, the TUSB544 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 = H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.

The Disconnect mode is the state in which TUSB544 has not detected far-end termination on both upstream facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of the four modes. The TUSB544 will remain in this mode until far-end receiver termination has been detected on both UFP and DFP. The TUSB544 will immediately exit this mode and enter U0 once far-end termination is detected.

Once in U0 mode, the TUSB544 will redrive all traffic received on UFP and DFP. U0 is the highest power mode of all USB3.1 modes. The TUSB544 will remain in U0 mode until electrical idle occurs on both UFP and DFP. Upon detecting electrical idle, the TUSB544 will immediately transition to U1.

The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB544’s UFP and DFP receiver termination will remain enabled. The UFP and DFP transmitter DC common mode is maintained. The power consumption in U1 will be similar to power consumption of U0.

Next to the disconnect mode, the U2 and U3 mode is next lowest power state. While in this mode, the TUSB544 will periodically perform far-end receiver detection. Anytime the far-end receiver termination is not detected on either UFP or DFP, the TUSB544 will leave the U2 and U3 mode and transition to the Disconnect mode. It will also monitor for a valid LFPS. Upon detection of a valid LFPS, the TUSB544 will immediately transition to the U0 mode. In U2 and U3 mode, the TUSB544’s receiver terminations will remain enabled but the TX DC common mode voltage will not be maintained.

When SLP_S0# is asserted low it will disable Receiver Detect functionality. While SLP_S0# is low and TUSB544 is in U2 and U3, TUSB544 will disable LOS and LFPS detection circuitry and RX termination for both channels will remain enabled. This allows even lower TUSB544 power consumption while in the U2 and U3 mode. Once SLP_S0# is asserted high, the TUSB544 will again start performing far-end receiver detection as well as monitor LFPS so it can know when to exit the U2 and U3 mode.

When SLP_S0# is asserted low and the TUSB544 is in Disconnect mode, the TUSB544 will remain in Disconnect mode and never perform far-end receiver detection. This allows even lower TUSB544 power consumption while in the Disconnect mode. Once SLP_S0# is asserted high, the TUSB544 will again start performing far-end receiver detection so it can know when to exit the Disconnect mode.