Route SSTXP/N, SSRXP/N, RX1P/N, RX2PN, TX1P/N, and TX2P/N pairs with controlled 90Ω differential impedance (±10%).
Route DP[3:0]P/N pairs with controlled 90Ω differential impedance (±10%).
There is no inter-pair length match requirement between SSTXP/N and SSRXP/N.
Keep the inter-pair matching between DP lanes (DP[3:0]) from GPU through TUSB5461-Q1 to the USB-C receptacle to less than 100 mils.
Keep away from other high speed signals.
Keep intra-pair routing (between P and N) to less than 5 mils.
Make sure length matching is near the location of mismatch.
Separate each pair by at least 3 times the signal trace width.
Keep the use of bends in differential traces to a
minimum. When bends are used, make sure the number of left and right bends are
as equal as possible and that the angle of the bend is≥ 135 degrees. This will
minimize any length mismatch causes by the bends and therefore minimize the
impact bends have on EMI.
Route all differential pairs on the same of layer.
Keep the number of vias to a minimum. TI
recommends to keep the vias count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do not route differential pairs over any plane split.
Adding test points can cause impedance discontinuity, and therefore, negatively impact signal performance. If test points are used, place the test points in series and symmetrically. Do not place test points in a manner that can cause a stub on the differential pair.
TI highly recommends to have reference plane void under the SuperSpeed pins of the USB-C receptacle to minimize the capacitance effect of the receptacle.
TI highly recommends to have reference plane void under the AC-coupling capacitances.