SLLSFZ6 November   2024 TUSB5461-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB5461-Q1 I2C Address Options
      4. 6.5.4 TUSB5461-Q1 I2C Target Behavior
  9. 7 Register Maps
    1. 7.1 TUSB5461-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Control I/O DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4-level Inputs
IIH High level input current VCC = 3.6V; VIN = 3.6V 20 60 µA
IIL Low level input current VCC = 3.6V; VIN = 0V –100 -40 µA
4-Level VTH Threshold 0 / R VCC = 3.3V 0.55 V
4-Level VTH Threshold R/ Float VCC = 3.3V 1.65 V
4-Level VTH Threshold Float / 1 VCC = 3.3V 2.7 V
RPU Internal pullup resistance 48 kΩ
RPD Internal pulldown resistance 98 kΩ
2-State CMOS Input (CTL0, CTL1, FLIP). CTL0 and FLIP are Failsafe.
VIH High-level input voltage VCC = 3.0V 2 3.6 V
VIL Low-level input voltage VCC = 3.6V 0 0.8 V
RPD Internal pulldown resistance for HPDIN, CADSNK 400 500 600 kΩ
RPD Internal pulldown resistance for CTL1 400 500 600 kΩ
IIH_CTL1 High-level input current for CTL1 VIN = 3.6V –11 11 µA
IIL_CTL1 Low-level input current for CTL1 VIN = GND, VCC = 3.6V –1 1 µA
IIH_HPD_CAD High-level input current for HPDIN, CADSNK VIN = 3.6V –11 11 µA
IIL_HPD_CAD Low-level input current for HPDIN, CADSNK VIN = GND, VCC = 3.6V –1 1 µA
IIH_CTL0_FLIP High-level input current for CTL0 and FLIP VIN = 3.6V; I2C_EN = 0 –1 1 µA
IIL_CTL0_FLIP Low-level input current for CTL0 and FLIP VIN = GND, VCC = 3.6V; I2C_EN = 0; –1 1 µA
I2C Control Pins (SCL, SDA)
VIH_3p3V High-level input voltage when configured for 3.3V I2C level I2C_EN = 1 2.0 3.6 V
VIL_3p3V Low-level input voltage when configured for 3.3V I2C level I2C_EN = 1 0 0.8 V
VIH_1p8V High-level input voltage when configured for 1.8V I2C level I2C_EN = F 1.2 V
VIL_1p8V Low-level input voltage when configured for 1.8V I2C level I2C_EN = F 0 0.6 V
VOL Low-level output voltage I2C_EN = 0; IOL = 6mA 0 0.4 V
IOL Low-level output current I2C_EN = 0; VOL = 0.4V 20 mA
II(I2C) Input current 0.1 × V(I2C) < Input voltage < 3.3V –1 1 µA
CI(I2C) Input capacitance 10 pF
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz) 150 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400kHz) 150 pF
R(EXT_I2C_FM+) External resistors on both SDA and SCL when operating at FM+ (1MHz) C(I2C_FM+_BUS) = 150pF 620 820 910 Ω
R(EXT_I2C_FM) External resistors on both SDA and SCL when operating at FM (400kHz) C(I2C_FM_BUS) = 150pF 620 1500 2200 Ω