SLLSFO9A May   2024  – September 2024 TUSB564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E

The TUSB564-Q1 device can be used in a system that handles DisplayPort UFP_D Pin Assignment E use-case if special measures are taken as described below. With UFP_D Pin Assignment E, the polarity of both the main link and AUX signals are inverted on the Type-C receptacle pins relative to Pin Assignment C. Moreover, on the Type-C receptacle, the location of Lane 0 is swapped with Lane 1 and that of Lane 2 is swapped with Lane 3 relative to Pin Assignment C. For correct reception of the DisplayPort video signal, the system must comprehend the above-described signaling variation.

The use of the TUSB564-Q1 device in a system that handles Pin Assignment E depends on whether AUX-to-SBU switching of the DisplayPort AUX signal is performed internally by the TUSB564-Q1 or by external devices such as a PD controller. It also depends on the configuration mode used: I2C Mode or GPIO Mode. In all those scenarios, the TUSB564-Q1 passes the polarity of the Main Link signals as received. The DisplayPort sink must handle the polarity inversion of those signals. Moreover, the DisplayPort sink must handle the lane swapping with the following lane-to-pin mapping as received by the TUSB564-Q1 device: Lane 0 → DP1, Lane 1 → DP0, Lane 2 → DP3, and Lane 3 → DP2.

The use-case with the AUX-to-SBU switching performed internally by the TUSB564-Q1 device is shown in Figure 8-3. If the TUSB564-Q1 device configuration is through the I2C Mode, AUX snooping must be disabled by setting AUX_SNOOP_DISABLE register 0x13[7] = 1'b1, and manual AUX-to-SBU switching must be performed through the AUX_SBU_OVR register 0x13[5:4]: AUX_SBU_OVR = 2’b01 for normal USB Type-C plug orientation, or AUX_SBU_OVR = 2’b10 for flipped USB Type-C plug orientation when Pin Assignment E signals are received. If the TUSB564-Q1 device configuration is through the GPIO Mode, all four DisplayPort lanes are automatically activated. The DisplayPort sink device must handle the polarity inversion of both the AUX and Main Link signals as well as main link lane swapping.

TUSB564-Q1 DisplayPort AUX Connections for UFP_D Pin Assignment E with Internal AUX SwitchingFigure 8-3 DisplayPort AUX Connections for UFP_D Pin Assignment E with Internal AUX Switching

The use-case with the AUX-to-SBU switching performed by an external device is shown in Figure 8-4. In this case, it is assumed that the PD controller is capable of correcting the polarity inversion of the AUX signal and the TUSB564-Q1 is provided with the corrected polarity of the AUX signal through its AUXp/AUXn pins. If the TUSB564-Q1 device configuration is through the I2C Mode, disable AUX snooping by setting AUX_SNOOP_DISABLE register 0x13[7] = 1'b1. The DisplayPort sink device must handle the polarity inversion of the Main Link signals as well as the Main Link lane swapping.

TUSB564-Q1 DisplayPort AUX Connections for UFP_D Pin Assignment E with External AUX SwitchingFigure 8-4 DisplayPort AUX Connections for UFP_D Pin Assignment E with External AUX Switching