SLLSFO9A May   2024  – September 2024 TUSB564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TUSB564-Q1 RGF Package, 40-Pin (VQFN) (Top View)Figure 4-1 RGF Package, 40-Pin (VQFN) (Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
DP0p32Diff ODP differential positive output for DisplayPort Lane 0.
DP0n31Diff ODP differential negative output for DisplayPort Lane 0.
DP1p29Diff ODP differential positive output for DisplayPort Lane 1.
DP1n28Diff ODP differential negative output for DisplayPort Lane 1.
DP2p26Diff ODP differential positive output for DisplayPort Lane 2.
DP2n25Diff ODP differential negative output for DisplayPort Lane 2.
DP3p23Diff ODP differential positive output for DisplayPort Lane 3.
DP3n22Diff ODP differential negative output for DisplayPort Lane 3.
TX1n2Diff I/ODifferential negative input for DisplayPort or differential negative output for USB3.2 upstream facing port.
TX1p1Diff I/ODifferential positive input for DisplayPort or differential positive output for USB3.2 upstream facing port.
RX1n5Diff IDifferential negative input for DisplayPort or USB3 upstream facing port.
RX1p4Diff IDifferential positive input for DisplayPort or USB3 upstream facing port.
RX2p8Diff IDifferential positive input for DisplayPort or USB3 upstream facing port.
RX2n7Diff IDifferential negative input for DisplayPort or USB3 upstream facing port.
TX2p11Diff I/ODifferential positive input for DisplayPort or differential positive output for USB3 upstream Facing port.
TX2n10Diff I/ODifferential negative input for DisplayPort or differential negative output for USB3 upstream Facing port.
SSTXp40Diff IDifferential positive input for USB3 downstream facing port.
SSTXn39Diff IDifferential negative input for USB3 downstream facing port.
SSRXp37Diff ODifferential positive output for USB3 downstream facing port.
SSRXn36Diff ODifferential negative output for USB3 downstream facing port.
EQ164 Level IThis pin along with EQ0 sets the USB receiver equalizer gain for upstream facing RX1 and RX2 when USB used. Up to 11dB of EQ available.
EQ034 Level IThis pin along with EQ1 sets the USB receiver equalizer gain for upstream facing RX1 and RX2 when USB used. Up to 11dB of EQ available.
EN212 Level I
(PD)		Device Enable. For normal operation pull up this pin to 3.3V through a 10k to 50kΩ resistor.
HPDIN242 Level IHot Plug Detect. This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch remains closed.
I2C_EN94 Level II2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is "0".
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3V.
SBU116I/O, CMOSSBU1. DC couple this pin to the SBU1 pin on the Type-C receptacle. A 2MΩ resistor to GND is also recommended.
SBU217I/O, CMOSSBU2. DC couple this pin to the SBU2 pin on the Type-C receptacle. A 2MΩ resistor to GND is also recommended.
AUXp18I/O, CMOSAUXp. DisplayPort AUX positive I/O connected to the DisplayPort sink through a AC-coupling capacitor. In addition to AC-coupling capacitor, this pin also requires a 1M resistor to DP_PWR (3.3V). This pin along with AUXN is used by the TUSB564-Q1 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
AUXn19I/O, CMOSAUXn. DisplayPort AUX negative I/O connected to the DisplayPort sink through a AC-coupling capacitor. In addition to AC-coupling capacitor, this pin also requires a 1M resistor to GND. This pin along with AUXP is used by the TUSB564-Q1 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
DPEQ1344 Level IDisplayPort Receiver EQ. The DPEQ1 and DPEQ0 pins select the DisplayPort receiver equalization gain.
DPEQ0/A1274 Level IDisplayPort Receiver EQ. The DPEQ0 and DPEQ1 pins select the DisplayPort receiver equalization gain. When I2C_EN ≠ "0", the DPEQ0 pin also sets the TUSB564-Q1 I2C address.
SSEQ1354 Level IThe SSEQ1 and SSEQ0 pins set the USB receiver equalizer gain for downstream facing SSTXP/N.
SSEQ0/A0304 Level IThe SSEQ0 and SSEQ1 pins set the USB receiver equalizer gain for downstream facing SSTXP/N. When I2C_EN ≠ "0", the SSEQ0 pin also sets the TUSB564-Q1 I2C address. If I2C_EN = "F", then the SSEQ0 pin must be set to "F" or "0".
FLIP/SCL132 Level I
(Failsafe)
(PD)		When I2C_EN = "0" this pin is Flip control, otherwise this pin is I2C clock. When used for the I2C clock, pull up to the VCC I2C supply on the I2C controller through an external resistor.
CTL0/SDA142 Level I
(Failsafe)
(PD)		When I2C_EN = "0" this pin is USB3 switch control, otherwise this pin is I2C data. When used for I2C data, pull up to the VCC I2C supply on the I2C controller through an external resistor.
CTL1152 Level I
(Failsafe)
(PD)		DP Alt mode Switch Control Pin. When I2C_EN = "0", this pin can enable or disable DisplayPort functionality. Otherwise, when I2C_EN ≠ "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
VCC12P3.3V Power Supply
VCC20P3.3V Power Supply
VCC38P3.3V Power Supply
NC33NCNo connect pin. Leave open.
GNDThermal PadGGround
(1) I = input, O = output, Diff = differential, P = power, NC = no connection, G = ground