SLLSFO9A May   2024  – September 2024 TUSB564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 DisplayPort

The TUSB564-Q1 supports up to four DisplayPort lanes at datarates up to 8.1Gbps (HBR3). When configured in DisplayPort mode, the TUSB564-Q1 monitors the native AUX traffic as the device traverses between DisplayPort source and DisplayPort sink. For the purposes of reducing power, the TUSB564-Q1 manages the number of active DisplayPort lanes based on the content of the AUX transactions. The TUSB564-Q1 snoops native AUX writes to DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE) of the DisplayPort sink. The TUSB564-Q1 disables or enables lanes based on value written to LANE_COUNT_SET. The TUSB564-Q1 disables all lanes when SET_POWER_STATE is in the D3. Otherwise, active lanes are based on value of LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE register. After AUX snoop is disabled, management of TUSB564-Q1 DisplayPort lanes are controlled through various configuration registers.

Note:

AUX snooping feature is only supported when TUSB564-Q1 is configured for I2C mode. When TUSB564-Q1 is configured for GPIO mode, the AUX snoop feature is disabled and all four DP lanes are enabled if HPDIN is asserted high.

When the TUSB564-Q1 AUX snoop feature is enabled, the syncs defined by the DisplayPort standard must be received for AUX snoop feature to function properly. AUX writes to the DPCD address 0x00600 and 0x00101 of the panel can result in SET_POWER_STATE and LANE_COUNT_SET fields at TUSB564-Q1 offset 0x12 to get set to the appropriate value. If these fields do not get set correctly, then incoming AUX may not be compliant. If this is the case, then it is best to disable AUX snoop by setting the AUX_SNOOP_DISABLE field at offset 0x13.