SLLSFO9 May   2024 TUSB564-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 PCB Insertion Loss Curves
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUXp/n and SBU1/2
TAUX_PD Switch propagation delay 1400 ps
TAUX_SW_OFF Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. 7500 ns
TAUX_SW_ON Switching time CTL1 to switch ON 3000 ns
TAUX_INTRA Intra-pair output skew 400 ps
USB3.1 and DisplayPort mode transition requirement (GPIO mode)
TGP_USB_4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa 4 µs
TCTL1_DEBOUNCE CTL1 and HPDIN debounce time when transitioning from H to L 3 10 ms
I2C (SDA and SCL)
fSCL I2C clock frequency 1 MHz
tBUF Bus free time between START and STOP conditions 0.5 µs
tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs
tLOW Low period of the I2C clock 0.5 µs
tHIGH High period of the I2C clock 0.26 µs
tSUSTA Setup time for a repeated START condition 0.26 µs
tHDDAT Data hold time 0 µs
tSUDAT Data setup time 50 ns
tR Rise time of both SDA and SCL signals 120 ns
tF Fall time of both SDA and SCL signals 20 × (VI2C/5.5 V) 120 ns
tSUSTO Setup time for STOP condition 0.26 µs
Cb Capacitive load for each bus line 100 pF