SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Link Control Register indicates is used to control link specific behavior.
PCI register offset: 80h
Register type: Read-only, Read/Write
Default value: 0000h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:9 | RSVD | r | Reserved. Returns zeros when read. |
8 | EN_CPM | rw | Enable Clock Power Management. |
7 | ES | rw | Extended Synch. |
6 | CCC | rw | Common Clock Configuration. This bit is set when a common clock is provided to both ends of the PCI Express link. This bit is also used to select the L0s exit latency and L1 exit latency. 0 – Reference clock is asynchronous (L0s exit latency and L1 exit latency based on the L0s_EXIT_LAT_ASYNC and L1_EXIT_LAT_ASYNC fields in the General Control Register 0) 1 – Reference clock is synchronous (L0s exit latency and L1 exit latency based on the L0s_EXIT_LAT_COMMON and L1_EXIT_LAT_COMMON fields in the General Control Register 0) |
5 | RL | r | Retrain Link. This bit has no function and is read only zero. |
4 | LD | r | Link Disable. This bit has no function and is read only zero. |
3 | RCB | rw | Read Completion Boundary. |
2 | RSVD | r | Reserved. Returns zero when read. |
1:0 | ASLPMC | rw | Active State Link PM Control. This field is used to enable and disable active state PM. 00 – Active State PM Disabled 01 – L0s Entry Enabled 10 – L1 Entry Enabled 11 – L0s and L1 Entry Enable |