SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register indicates the command to be executed by the TUSB73X0.
Operational Base register offset: 00h
Register type: Read-Only, Read/Write
Default value: 0000 0000h
Bit No. | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
31:12 | RSVD | r | Reserved. Returns zeros when read. |
11 | EU3S | rw | Enable U3 MFINDEX Stop |
10 | EWE | rw | Enable Wrap Event |
9 | CRS | rw | Controller Restore State |
8 | CSS | rw | Controller Save State |
7 | LHCRST | rw | Light Host Controller Reset |
6:4 | RSVD | r | Reserved. Returns zeros when read. |
3 | HSEE | rw | Host System Error Enable |
2 | INTE | rw | Interrupter Enable |
1 | HCRST | rw | Host Controller Reset |
0 | R/S | rw | Run/Stop. |