SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Link Status Register indicates current state of the PCI Express Link.
PCI register offset: 82h
Register type: Read-only
Default value: 101xh
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | x | x |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15 | LINK_ABS | r | Link Autonomous Bandwidth Status. This bit has no function and is read only zero. |
14 | LINK_BMS | r | Link Bandwidth Management Status. This bit has no function and is read only zero. |
13 | DLL_ACTIVE | r | Data Link Layer Active. This bit has no function and is read only zero. |
12 | SCC | r | Slot Clock Configuration. This bit is 1, because the TUSB73X0 uses the 100-MHz differential reference clock provided by the platform. |
11 | LT | r | Link Training. This bit has no function and is read only zero. |
10 | TE | r | Retrain Link. This bit has no function and is read only zero. |
9:4 | NLW | r | Negotiated Link Width. This field is read only 000001b indicating the lane width is 1x. |
3:0 | LS | r | Link Speed. This field indicates the negotiated link speed. |