SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Uncorrectable Error Mask Register controls the reporting of individual errors as they occur. When a bit is set to one, the corresponding error condition will not be logged, and does not update any of the status bits within the Extended Error Reporting Capability block.
PCI Express Extended Register Offset: 108h
Register type: Read-Only, Read/Write
Default value: 0000 0000h
Bit No. | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
31:21 | RSVD | r | Reserved. Returns zeros when read. |
20 | UR_ERROR_MASK(1) | rw | Unsupported Request Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
19 | ECRC_ERROR_MASK(1) | rw | Extended CRC Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
18 | MAL_TLP_MASK(1) | rw | Malformed TLP Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
17 | RX_OVERFLOW_MASK(1) | rw | Receiver Overflow Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
16 | UNXP_CPL_MASK(1) | rw | Unexpected Completion Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
15 | CPL_ABORT_MASK(1) | rw | Completer Abort Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
14 | CPL_TIMEOUT_MASK(1) | rw | Completion Timeout Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
13 | FC_ERROR_MASK(1) | rw | Flow Control Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
12 | PSN_TLP_MASK(1) | rw | Poisoned TLP Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
11:5 | RSVD | r | Reserved. Returns zeros when read. |
4 | DLL_ERROR_MASK(1) | rw | Data Link Protocol Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked |
3:0 | RSVD | r | Reserved. Returns zeros when read. |