SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register determines and changes the current power state of the TUSB73X0.
PCI register offset: 44h
Register type: Read/Write, Read-only
Default value: 0008h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15 | PME_STAT | rc | PME# Status. This bit is sticky and is only reset by a Global Reset. |
14:13 | DATA_SCALE | r | Data Scale. This 2-bit field returns 0’s when read because the TUSB73X0 does not use the Data Register. |
12:9 | DATA_SEL | r | Data Select. This 4-bit field returns 0’s when read because the TUSB73X0 does not use the Data Register. |
8 | PME_EN | rw | PME# Enable. This bit is sticky and is only reset by a Global Reset. |
7:4 | RSVD | r | Reserved. Returns zero when read. |
3 | NO_SOFT_RESET | r | No Soft Reset. This bit returns 1 indicating that no internal reset is generated and the device retains its configuration context when transitioning from the D3hot state to the D0 state. |
2 | RSVD | r | Reserved. Returns zero when read. |
1:0 | PWR_STATE | rw | Power State. This 2-bit field is used both to determine the current power state of the function and to set the function into a new power state. This field is encoded as follows:00 = D001 = D110 = D211 = D3hot. |