SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register is used to read the state of the GPIO pins and to change the state of GPIO pins that are in output mode. Writing to a bit that is in input mode will be ignored. The default value at power up depends on the state of the GPIO terminals as they default to general purpose inputs. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset.
PCI register offset: B6h
Register type: Read/Write, Read-Only
Default value: 0000h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | x | x | x |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:4 | RSVD | r | Reserved. Returns zero when read. |
3 | GPIO3_DATA(1) | rw | GPIO 3 Data. This bit is used to read the state of GPIO3 or change the state of GPIO3 in output mode. |
2 | GPIO2_DATA(1) | rw | GPIO 2 Data. This bit is used to read the state of GPIO2 or change the state of GPIO2 in output mode. |
1 | GPIO1_DATA(1) | rw | GPIO 1 Data. This bit is used to read the state of GPIO1 or change the state of GPIO1 in output mode. |
0 | GPIO0_DATA(1) | rw | GPIO 0 Data. This bit is used to read the state of GPIO0 or change the state of GPIO0 in output mode. |