SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Command register provides control over the TUSB73X0 interface to the PCIe interface
PCI register offset: 04h
Register type: Read-only, Read/Write
Default value: 0000h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:11 | RSVD | r | Reserved. Returns zeros when read. |
10 | INT_DISABLE | rw | INTx# Disable. This bit enables device specific interrupts. |
9 | FBB_ENB | r | Fast back-to-back enable. The host controller does not generate fast back-to-back transactions; therefore, this bit returns 0 when read. |
8 | SERR_ENB | rw | SERR enable bit. When this bit is set, the host controller can signal fatal and nonfatal errors on the PCI Express interface on behalf of SERR assertions detected on the PCI bus. 0 = Disable the reporting of nonfatal errors and fatal errors (default) 1 = Enable the reporting of nonfatal errors and fatal errors |
7 | STEP_ENB | r | Address/data stepping control. The host controller does not support address/data stepping, and this bit is hardwired to 0b. |
6 | PERR_ENB | rw | Controls the setting of bit 8 (DATAPAR) in the status register
(offset 06h, see Status Register) in response to a received poisoned TLP from PCI Express.
A received poisoned TLP is forwarded with bad parity to conventional
PCI regardless of the setting of this bit. 0 = Disables the setting of the controller data parity error bit (default) 1 = Enables the setting of the controller data parity error bit |
5 | VGA_ENB | r | VGA palette snoop enable. The host controller does not support VGA palette snooping; therefore, this bit returns 0b when read. |
4 | MWI_ENB | r | Memory write and invalidate enable. The host controller does not support memory write and invalidate enable; therefore, this bit returns 0b when read. |
3 | SPECIAL | r | Special cycle enable. This host controller does not respond to special cycle transactions; therefore, this bit returns 0 when read. |
2 | CONTROLLER_ENB | rw | Bus controller enable. When this bit is set, the host controller is enabled to initiate transactions on the PCI Express interface. 0 = PCI Express interface cannot initiate transactions. The host controller must disable the response to memory and I/O transactions on the PCI interface (default). 1 = PCI Express interface can initiate transactions. The host controller can forward memory and I/O transactions from PCI secondary interface to the PCI Express interface. |
1 | MEMORY_ENB | rw | Memory space enable. Setting this bit enables the host controller to respond to memory transactions on the PCI Express interface. 0 = PCI Express receiver cannot process downstream memory transactions and must respond with an unsupported request (default) 1 = PCI Express receiver can process downstream memory transactions. The host controller can forward memory transactions to the PCI interface. |
0 | IO_ENB | r | I/O space enable. Setting this bit enables the host controller to respond to I/O transactions on the PCI Express interface. 0 = PCI Express receiver cannot process downstream I/O transactions and must respond with an unsupported request (default) 1 = PCI Express receiver can process downstream I/O transactions. The host controller can forward I/O transactions to the PCI interface. |