SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register is used to control the direction of the eight GPIO pins. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset.
PCI register offset: B4h
Register type: Read/Write, Read-Only
Default value: 0000h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:4 | RSVD | r | Reserved. Returns zero when read. |
3 | GPIO3_DIR(1) | rw | GPIO 3 Data Direction. This bit selects whether GPIO3 is in input or output mode. 0 – Input 1 – Output |
2 | GPIO2_DIR(1) | rw | GPIO 2 Data Direction. This bit selects whether GPIO2 is in input or output mode. 0 – Input 1 – Output |
1 | GPIO1_DIR(1) | rw | GPIO 1 Data Direction. This bit selects whether GPIO1 is in input or output mode. 0 – Input 1 – Output |
0 | GPIO0_DIR(1) | rw | GPIO 0 Data Direction. This bit selects whether GPIO0 is in input or output mode. 0 – Input 1 – Output |