SLLSE76Q March   2011  – March 2024 TUSB7320 , TUSB7340

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  3.3-V I/O Electrical Characteristics
    6. 5.6  Input Clock Specification
    7. 5.7  Input Clock 1.8-V DC Characteristics
    8. 5.8  Crystal Specification
    9. 5.9  TUSB7320 Power Consumption
    10. 5.10 TUSB7340 Power Consumption
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PHY Control
        1. 6.3.1.1 Output Voltage Swing Control
          1. 6.3.1.1.1 De-Emphasis Control
        2. 6.3.1.2 Adaptive Equalizer
      2. 6.3.2 Input Clock
        1. 6.3.2.1 Clock Source Requirements
        2. 6.3.2.2 External Clock
        3. 6.3.2.3 External Crystal
    4. 6.4 Programming
      1. 6.4.1 Two-Wire Serial-Bus Interface
        1. 6.4.1.1 Serial-Bus Interface Implementation
        2. 6.4.1.2 Serial-Bus Interface Protocol
        3. 6.4.1.3 Serial-Bus EEPROM Application
      2. 6.4.2 System Management Interrupt
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Features
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Upstream Implementation
        2. 7.2.2.2 Downstream Ports Implementation
        3. 7.2.2.3 PCI Express Connector
        4. 7.2.2.4 1.1-V Regulator
        5. 7.2.2.5 5-V VBUS Options
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up and Power-Down Sequencing
        1. 7.3.1.1 Power-Up Sequence
        2. 7.3.1.2 Power-Down Sequence
      2. 7.3.2 PCI Express Power Management
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 High-Speed Differential Routing
        2. 7.4.1.2 SuperSpeed Differential Routing
      2. 7.4.2 Layout Example
  9. 8 Register Maps
    1. 8.1 Classic PCI Configuration Space
      1. 8.1.1  The PCI Configuration Map
      2. 8.1.2  Vendor ID Register
      3. 8.1.3  Device ID Register
      4. 8.1.4  Command Register
      5. 8.1.5  Status Register
      6. 8.1.6  Class Code and Revision ID Register
      7. 8.1.7  Cache Line Size Register
      8. 8.1.8  Latency Timer Register
      9. 8.1.9  Header Type Register
      10. 8.1.10 BIST Register
      11. 8.1.11 Base Address Register 0
      12. 8.1.12 Base Address Register 1
      13. 8.1.13 Base Address Register 2
      14. 8.1.14 Base Address Register 3
      15. 8.1.15 Subsystem Vendor ID Register
      16. 8.1.16 Subsystem ID Register
      17. 8.1.17 Capabilities Pointer Register
      18. 8.1.18 Interrupt Line Register
      19. 8.1.19 Interrupt Pin Register
      20. 8.1.20 Min Grant Register
      21. 8.1.21 Max Latency Register
      22. 8.1.22 Capability ID Register
      23. 8.1.23 Next Item Pointer Register
      24. 8.1.24 Power Management Capabilities Register
      25. 8.1.25 Power Management Control/Status Register
      26. 8.1.26 Power Management Bridge Support Extension Register
      27. 8.1.27 Power Management Data Register
      28. 8.1.28 MSI Capability ID Register
      29. 8.1.29 Next Item Pointer Register
      30. 8.1.30 MSI Message Control Register
      31. 8.1.31 MSI Lower Message Address Register
      32. 8.1.32 MSI Upper Message Address Register
      33. 8.1.33 MSI Message Data Register
      34. 8.1.34 Serial Bus Release Number Register (SBRN)
      35. 8.1.35 Frame Length Adjustment Register (FLADJ)
      36. 8.1.36 PCI Express Capability ID Register
      37. 8.1.37 Next Item Pointer Register
      38. 8.1.38 PCI Express Capabilities Register
      39. 8.1.39 Device Capabilities Register
      40. 8.1.40 Device Control Register
      41. 8.1.41 Device Status Register
      42. 8.1.42 Link Capabilities Register
      43. 8.1.43 Link Control Register
      44. 8.1.44 Link Status Register
      45. 8.1.45 Device Capabilities 2 Register
      46. 8.1.46 Device Control 2 Register
      47. 8.1.47 Link Control 2 Register
      48. 8.1.48 Link Status 2 Register
      49. 8.1.49 Serial Bus Data Register
      50. 8.1.50 Serial Bus Index Register
      51. 8.1.51 Serial Bus Target Address Register
      52. 8.1.52 Serial Bus Control and Status Register
      53. 8.1.53 GPIO Control Register
      54. 8.1.54 GPIO Data Register
      55. 8.1.55 MSI-X Capability ID Register
      56. 8.1.56 Next Item Pointer Register
      57. 8.1.57 MSI-X Message Control Register
      58. 8.1.58 MSI-X Table Offset and BIR Register
      59. 8.1.59 MSI-X PBA Offset and BIR Register
      60. 8.1.60 Subsystem Access Register
      61. 8.1.61 General Control 0 Register
      62. 8.1.62 General Control 1 Register
      63. 8.1.63 General Control 2 Register
      64. 8.1.64 USB Control Register
      65. 8.1.65 De-Emphasis and Swing Control Register
      66. 8.1.66 Equalizer Control Register
      67. 8.1.67 Custom PHY Transmit/Receive Control Register
    2. 8.2 PCI Express Extended Configuration Space
      1. 8.2.1  The PCI Express Extended Configuration Map
      2. 8.2.2  Advanced Error Reporting Capability Register
      3. 8.2.3  Next Capability Offset / Capability Version Register
      4. 8.2.4  Uncorrectable Error Status Register
      5. 8.2.5  Uncorrectable Error Mask Register
      6. 8.2.6  Uncorrectable Error Severity Register
      7. 8.2.7  Correctable Error Severity Register
      8. 8.2.8  Correctable Error Mask Register
      9. 8.2.9  Advanced Error Capabilities and Control Register
      10. 8.2.10 Header Log Register
      11. 8.2.11 Device Serial Number Capability ID Register
      12. 8.2.12 Next Capability Offset/Capability Version Register
      13. 8.2.13 Device Serial Number Register
    3. 8.3 xHCI Memory Mapped Register Space
      1. 8.3.1 The xHCI Register Map
      2. 8.3.2 Host Controller Capability Registers
        1. 8.3.2.1 Capability Registers Length
        2. 8.3.2.2 Host Controller Interface Version Number
        3. 8.3.2.3 Host Controller Structural Parameters 1
        4. 8.3.2.4 Host Controller Structural Parameters 2
        5. 8.3.2.5 Host Controller Structural Parameters 3
        6. 8.3.2.6 Host Controller Capability Parameters
        7. 8.3.2.7 Doorbell Offset
        8. 8.3.2.8 Runtime Register Space Offset
      3. 8.3.3 Host Controller Operational Registers
        1. 8.3.3.1  USB Command Register
        2. 8.3.3.2  USB Command Register
        3. 8.3.3.3  USB Status Register
        4. 8.3.3.4  Page Size Register
        5. 8.3.3.5  Device Notification Control Register
        6. 8.3.3.6  Command Ring Control Register
        7. 8.3.3.7  Device Context Base Address Array Pointer Register
        8. 8.3.3.8  Configure Register
        9. 8.3.3.9  Port Status and Control Register
        10. 8.3.3.10 Port PM Status and Control Register (USB 3.0 Ports)
        11. 8.3.3.11 Port PM Status and Control Register (USB 2.0 Ports)
        12. 8.3.3.12 Port Link Info Register
      4. 8.3.4 Host Controller Runtime Registers
        1. 8.3.4.1 Microframe Index Register
        2. 8.3.4.2 Interrupter Management Register
        3. 8.3.4.3 Interrupter Moderation Register
        4. 8.3.4.4 Event Ring Segment Table Size Register
        5. 8.3.4.5 Event Ring Segment Table Base Address Register
        6. 8.3.4.6 Event Ring Dequeue Pointer Register
      5. 8.3.5 Host Controller Doorbell Registers
      6. 8.3.6 xHCI Extended Capabilities Registers
        1. 8.3.6.1 USB Legacy Support Capability Register
        2. 8.3.6.2 USB Legacy Support Control/Status Register
        3. 8.3.6.3 xHCI Supported Protocol Capability Register (USB 2.0)
        4. 8.3.6.4 xHCI Supported Protocol Name String Register (USB 2.0)
        5. 8.3.6.5 xHCI Supported Protocol Port Register (USB 2.0)
        6. 8.3.6.6 xHCI Supported Protocol Capability Register (USB 3.0)
        7. 8.3.6.7 xHCI Supported Protocol Name String Register (USB 3.0)
        8. 8.3.6.8 xHCI Supported Protocol Port Register (USB 3.0)
    4. 8.4 MSI-X Memory Mapped Register Space
      1. 8.4.1 The MSI-X Table and PBA in Memory Mapped Register Space
    5. 8.5 The MSI-X Table and PBA in Memory Mapped Register Space
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.1.3 Serial-Bus EEPROM Application

A serial EEPROM interface is implemented to pre-load several registers. The registers and corresponding bits that are loaded through the EEPROM are provided in Table 6-4.

Table 6-4 EEPROM Register Loading Map
SERIAL EEPROM WORD ADDRESSBYTE DESCRIPTION
00hTUSB73X0 Function Indicator (00h)
01hNumber of Bytes (19h)
02hPCI D0h, Subsystem Vendor ID, Byte 0
03hPCI D1h, Subsystem Vendor ID, Byte 1
04hPCI D2h, Subsystem ID, Byte 0
05hPCI D3h, Subsystem ID, Byte 1
06hPCI D4h, General Control 0, Byte 0
07hPCI D5h, General Control 0, Byte 1
08hPCI D8h, General Control 1, Byte 0
09hPCI DCh, General Control 2, Byte 0
0AhPCI E0h, USB Control, Byte 0
0BhPCI E1h, USB Control, Byte 1
0ChPCI E2h, USB Control, Byte 2
0DhPCI E3h, USB Control, Byte 3
0EhPCI E4h, De-emphasis and Swing Control, Byte 0
0FhPCI E5h, De-emphasis and Swing Control, Byte 1
10hPCI E6h, De-emphasis and Swing Control, Byte 2
11hPCI E7h, De-emphasis and Swing Control, Byte 3
12hPCI E8h, Equalizer Control, Byte 0
13hPCI E9h, Equalizer Control, Byte 1
14hPCI EAh, Equalizer Control, Byte 2
15hPCI EBh, Equalizer Control, Byte 3
16hPCI ECh, Custom PHY Transmit/Receive Control, Byte 0
17hPCI EDh, Custom PHY Transmit/Receive Control, Byte 1
18hPCI EEh, Custom PHY Transmit/Receive Control, Byte 2
19hPCI EFh, Custom PHY Transmit/Receive Control, Byte 3
1AhPCI 61h, Frame Length Adjustment Register
1BhEnd of List Indicator (80h)

This format must be explicitly followed for the host controller to correctly load initialization values from a serial EEPROM. All byte locations must be considered when programming the EEPROM.

The serial EEPROM is addressed by the host controller at target address 1010 000b. This target address is internally hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the EEPROM are tied to VSS to achieve this address. The serial EEPROM in the sample application circuit (Figure 6-2) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to VSS.

During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be monitored to verify a successful download.