SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset.
PCI register offset: D4h
Register type: Read/Write
Default value: 0000 0D9Bh
Bit No. | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
31:12 | RSVD | r | Reserved. Returns zeros when read. |
11:9 | L1_EXIT_LAT_ASYNC(1) | rw | L1 Exit Latency for Asynchronous Clock. This value in this field is the value reported in the L1_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 0. This field defaults to 110b. |
8:6 | L1_EXIT_LAT_COMMON(1) | rw | L1 Exit Latency for Common Clock. This value in this field is the value reported in the L1_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 1. This field defaults to 110b. |
5:3 | L0s_EXIT_LAT_ASYNC(1) | rw | L0s Exit Latency for Asynchronous Clock. This value in this field is the value reported in the L0s_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 0. This field defaults to 011b. |
2:0 | L0s_EXIT_LAT_COMMON(1) | rw | L0s Exit Latency for Common Clock. This value in this field is the value reported in the L0s_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 1. This field defaults to 011b. |