The TUSB8020B is a two-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed USB and high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or low-speed connections on the downstream ports. When the upstream port is connected to an electrical environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is disabled on the downstream ports. When the upstream port is connected to an electrical environment that only supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the downstream ports.
The TUSB8020B supports per port or ganged power switching and overcurrent protection.
An individually port power controlled hub switches power on or off to each downstream port as requested by the USB host. Also when an individually port power controlled hub senses an overcurrent event, only power to the affected downstream port will be switched off.
A ganged hub switches on power to all its downstream ports when power is required to be on for any port. The power to the downstream ports is not switched off unless all ports are in a state that allows power to be removed. Also when a ganged hub senses an overcurrent event, power to all downstream ports will be switched off.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TUSB8020B | HTQFP (48) | 7.00 mm × 7.00 mm |
Changes from B Revision (March 2017) to C Revision
Changes from A Revision (July 2014) to B Revision
Changes from * Revision (July 2004) to A Revision
The TUSB8020B downstream ports provide support for battery charging applications by providing battery charging connected downstream port (CDP) handshaking support. It also supports a dedicated charging port (DCP) mode when the upstream port is not connected. The DCP mode supports USB devices which support the USB Battery Charging and the Chinese Telecommunications Industry Standard YD/T 1591-2009. In addition, an automatic mode provides transparent support for BC devices and devices supporting Divider Mode charging solutions when the upstream port is unconnected.
The TUSB8020B provides terminal strap configuration for some features including battery charging support, and also provides customization though OTP ROM, I2C EEPROM or through an I2C/SMBus slave interface for PID, VID, and custom port and phy configurations. Custom string support is also available when using an I2C EEPROM or the I2C/SMBus slave interface.
The device is available in a 48-pin HTQFP package and is offered in a commercial version (TUSB8020B) for operation over the temperature range of 0°C to 70°C and in an industrial version (TUSB8020BI) for operation over the temperature range of –40°C to 85°C.
PIN | TYPE | DESCRIPTION | ||||||||
---|---|---|---|---|---|---|---|---|---|---|
NAME | NO. | |||||||||
CLOCK AND RESET SIGNALS | ||||||||||
GRSTz | 11 | I PU |
Global power reset. This reset brings all of the TUSB8020B internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional. | |||||||
XI | 38 | I | Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO. | |||||||
XO | 39 | O | Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO. | |||||||
USB UPSTREAM SIGNALS | ||||||||||
USB_SSTXP_UP | 29 | O | USB SuperSpeed transmitter differential pair (positive) | |||||||
USB_SSTXM_UP | 28 | O | USB SuperSpeed transmitter differential pair (negative) | |||||||
USB_SSRXP_UP | 32 | I | USB SuperSpeed receiver differential pair (positive) | |||||||
USB_SSRXM_UP | 31 | I | USB SuperSpeed receiver differential pair (negative) | |||||||
USB_DP_UP | 26 | I/O | USB high-speed differential transceiver (positive) | |||||||
USB_DM_UP | 27 | I/O | USB high-speed differential transceiver (negative) | |||||||
USB_R1 | 24 | I | Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND. | |||||||
USB_VBUS | 9 | I | USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-kΩ ±1% resistor, and to ground through a 10-kΩ ±1% resistor from the signal to ground. |
|||||||
USB DOWNSTREAM SIGNALS | ||||||||||
USB_SSTXP_DN1 | 43 | O | USB SuperSpeed transmitter differential pair (positive) downstream port 1. | |||||||
USB_SSTXM_DN1 | 44 | O | USB SuperSpeed transmitter differential pair (negative) downstream port 1. | |||||||
USB_SSRXP_DN1 | 46 | I | USB SuperSpeed receiver differential pair (positive) downstream port 1. | |||||||
USB_SSRXM_DN1 | 47 | I | USB SuperSpeed receiver differential pair (negative) downstream port 1. | |||||||
USB_DP_DN1 | 41 | I/O | USB high-speed differential transceiver (positive) downstream port 1. | |||||||
USB_DM_DN1 | 42 | I/O | USB high-speed differential transceiver (negative) downstream port 1. | |||||||
PWRCTL1/BATEN1 | 4 | I/O PD |
USB port 1 power-on control for downstream power or battery charging enable. The terminal is used for control of the downstream power switch for Port 1. | |||||||
In addition, the value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register. | ||||||||||
0 = Battery charging not supported 1 = Battery charging supported |
||||||||||
OVERCUR1z | 5 | I PU |
USB DS port 1 overcurrent detection input. This terminal is used to connect the over current output of the downstream port power switch for port 1. | |||||||
0 = An overcurrent event has occurred 1 = An overcurrent event has not occurred |
||||||||||
If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode, either OVERCUR1z or OVERCUR2z can be used. In ganged mode, the overcurrent will be reported as a hub event instead of a port event. | ||||||||||
USB_SSTXP_DN2 | 16 | O | USB SuperSpeed transmitter differential pair (positive) downstream port 2. | |||||||
USB_SSTXM_DN2 | 17 | O | USB SuperSpeed transmitter differential pair (negative) downstream port 2. | |||||||
USB_SSRXP_DN2 | 19 | I | USB SuperSpeed receiver differential pair (positive) downstream port 2. | |||||||
USB_SSRXM_DN2 | 20 | I | USB SuperSpeed receiver differential pair (negative) downstream port 2. | |||||||
USB_DP_DN2 | 14 | I/O | USB high-speed differential transceiver (positive) downstream port 2. | |||||||
USB_DM_DN2 | 15 | I/O | USB high-speed differential transceiver (negative) downstream port 2. | |||||||
PWRCTL2/BATEN2 | 6 | I/O PD |
Power-on control /battery charging enable for downstream port 2. This terminal is used for control of the downstream power switch for port 2. | |||||||
The value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for port 2 as indicated in the Battery Charging Support register. | ||||||||||
0 = Battery charging not supported 1 = Battery charging supported |
||||||||||
OVERCUR2z | 8 | I PU |
Overcurrent detection for downstream port 2. This terminal is used to connect the over current output of the downstream port power switch for port 2. | |||||||
0 = An overcurrent event has occurred 1 = An overcurrent event has not occurred |
||||||||||
If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode either OVERCUR1z or OVERCUR2z can be used. In ganged mode the overcurrent will be reported as a hub event instead of a port event. | ||||||||||
I2C/SMBUS SIGNALS | ||||||||||
SCL/SMBCLK | 2 | I/O PD |
I2C clock/SMBus clock. Function of terminal depends on the setting of the SMBUSz input. | |||||||
When SMBUSz = 1, this terminal acts as the serial clock interface for an I2C EEPROM. | ||||||||||
When SMBUSz = 0, this terminal acts as the serial clock interface for an SMBus host. | ||||||||||
This pin must be pulled up to use the OTP ROM. | ||||||||||
Can be left unconnected if external interface not implemented. | ||||||||||
SDA/SMBDAT | 3 | I/O PD |
I2C data/SMBus data. Function of terminal depends on the setting of the SMBUSz input. | |||||||
When SMBUSz = 1, this terminal acts as the serial data interface for an I2C EEPROM. | ||||||||||
When SMBUSz = 0, this terminal acts as the serial data interface for an SMBus host. | ||||||||||
This pin must be pulled up to use the OTP ROM. | ||||||||||
Can be left unconnected if external interface not implemented. | ||||||||||
TEST AND MISCELLANEOUS SIGNALS | ||||||||||
SMBUSz/SS_DN2 | 22 | I PU |
SMBUS mode / SuperSpeed USB Status for downstream port 2 | |||||||
The value of the terminal is sampled at the deassertion of reset to enable I2C or SMBus mode. | ||||||||||
0 = SMBus mode selected 1 = I2C mode selected |
||||||||||
After reset, this signal indicates the SuperSpeed USB connection status of downstream port 2. A value of 1 indicates the connection is SuperSpeed USB. | ||||||||||
PWRCTL_POL/SS_DN1 | 21 | I/O PD |
Power control polarity / SuperSpeed USB status for downstream port 1. | |||||||
The value of the terminal is sampled at the deassertion of reset to set the polarity of PWRCTL[2:1]. | ||||||||||
0 = PWRCTL polarity is active high. 1 = PWRCTL polarity is active low. |
||||||||||
After reset, this signal indicates the SuperSpeed USB connection status of downstream port 1. A value of 1 indicates the connection is SuperSpeed USB. | ||||||||||
GANGED/SMBA2/ HS_UP |
35 | I PU |
Ganged operation enable/SMBus address bit 2/ high-speed status for upstream port | |||||||
The value of the terminal is sampled at the deassertion of reset to set the power switch and over current detection mode as follows: | ||||||||||
0 = Individual power control supported when power switching is enabled. 1 = Power control gangs supported when power switching is enabled. |
||||||||||
When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 2. SMBus slave address bits 2 and 3 are always 1 for the TUSB8020B. | ||||||||||
After reset, this signal indicates the high-speed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a high-speed USB capable port. | ||||||||||
FULLPWRMGMTz/ SMBA1/SS_UP |
36 | I, PU | Full power management enable/ SMBus Address bit 1/ Super-Speed USB status for upstream port | |||||||
The value of the terminal is sampled at the deassertion of reset to set the power switch control follows: | ||||||||||
0 = Power switching supported 1 = Power switching not supported |
||||||||||
Full power management is the ability to control power to the downstream ports of the TUSB8020B using PWRCTL[2:1]/BATEN[2:1]. | ||||||||||
When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave address bit 3 is always 1 for the TUSB8020B. | ||||||||||
Can be left unconnected if full power management and SMBus are not implemented. | ||||||||||
After reset, this signal indicates the SuperSpeed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port. | ||||||||||
TEST | 10 | I PD |
TEST mode enable. When this terminal is asserted high at reset enables test mode. This terminal is reserved for factory use. It is recommended to pull-down this terminal to ground. | |||||||
POWER AND GROUND SIGNALS | ||||||||||
VDD | 1, 12, 18, 30, 34, 45 | PWR | 1.1-V power rail | |||||||
VDD33 | 7, 13, 23, 25, 33, 37, 40, 48 | PWR | 3.3-V power rail | |||||||
GND | PAD | — | Ground |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –65 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2000 | 2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | 500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD(1) | 1.1-V supply voltage | 0.99 | 1.1 | 1.26 | V | |
VDD33 | 3.3-V supply voltage | 3 | 3.3 | 3.6 | V | |
USB_VBUS | Voltage at USB_VBUS PAD | 0 | 1.155 | V | ||
TA | Operating free-air temperature range | TUSB8020B | 0 | 25 | 70 | °C |
TUSB8020BI | –40 | 25 | 85 | |||
TJ | Operating junction temperature range | –40 | 25 | 105 | °C |
THERMAL METRIC(1) | TUSB8020B | UNIT | |
---|---|---|---|
PHP | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 31.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 16.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 13 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 12.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.9 | °C/W |
PARAMETER | OPERATION | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VIH | High-level input voltage(1) | VDD33 | 2 | VDD33 | V | ||
VIL | Low-level input voltage(1) | VDD33 | 0 | 0.8 | V | ||
VI | Input voltage | 0 | VDD33 | V | |||
VO | Output voltage(2) | 0 | VDD33 | V | |||
tt | Input transition time (trise and tfall) | 0 | 25 | ns | |||
Vhys | Input hysteresis(3) | 0.13 × VDD33 | V | ||||
VOH | High-level output voltage | VDD33 | IOH = –4 mA | 2.4 | V | ||
VOL | Low-level output voltage | VDD33 | IOL = 4 mA | 0.4 | V | ||
IOZ | High-impedance, output current(2) | VDD33 | VI = 0 to VDD33 | ±20 | µA | ||
IOZP | High-impedance, output current with internal pullup or pulldown resistor(4) | VDD33 | VI = 0 to VDD33 | ±225 | µA | ||
II | Input current(5) | VDD33 | VI = 0 to VDD33 | ±15 | µA |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
td1 | VDD33 stable before VDD stable. No timing relationship between VDD33 and VDD | 0 | ms | ||
td2 | VDD and VDD33 stable before deassertion of GRSTZ. | 3 | ms | ||
tsu_io | Setup for MISC inputs sampled at the deassertion of GRSTZ(1) | 0.1 | µs | ||
thd_io | Hold for MISC inputs sampled at the deassertion of GRSTZ.(1) | 0.1 | µs | ||
tVDD33_RAMP | VDD33 supply ramp requirements | 0.2 | 100 | ms | |
tVDD_RAMP | VDD supply ramp requirements | 0.2 | 100 | ms |