7:2 | RSVD | RO | Reserved. Read only, returns 0 when read. |
1 | smbusRst | RSU | SMBus interface reset. This bit resets the SMBus target interface to its default state and loads the registers back to their GRSTz values. This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect. (Not used with I2C) |
0 | cfgActive | RCU | Configuration active. This bit indicates that configuration of the TUSB8040A1 is currently active. The bit is set by hardware when the device enters the I2C or SMBus mode. The TUSB8040A1 does not connect on the upstream port while this bit is 1.When in I2C mode, the bit is cleared by hardware when the TUSB8040A1 exits the I2C mode. When in the SMBus mode, this bit must be cleared by the SMBus host in order to exit the configuration mode and allow the upstream port to connect. The bit is cleared by a writing 1. A write of 0 has no effect. |