TUSB8041A Four-Port USB 3.1 Gen1 Hub
- SLLSEW3 August 2017 TUSB8041A
  
  PRODUCTION DATA.

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DATA SHEET

TUSB8041A Four-Port USB 3.1 Gen1 Hub

1 Features

Four Port USB 3.1 Gen1 Hub
USB 2.0 Hub Features
- Multi Transaction Translator (MTT) Hub: Four Transaction Translators
- Two Asynchronous Endpoint Buffers Per Transaction Translator
Supports Battery Charging:
- Supports D+/D- Divider Charging Port (ACP1, ACP2) when the Upstream Port is Unconnected or not Configured
- Supports Automatic Mode for Transition Between DCP or ACP Modes When the Upstream Port is Unconnected
- CDP Mode (Upstream Port Connected)
- DCP Mode (Upstream Port Unconnected)
- DCP Mode Complies with Chinese Telecommunications Industry Standard YD/T 1591-2009
Supports Operation as a USB 3.1 Gen1 or USB 2.0 Compound Device
Per Port or Ganged Power Switching and Over-Current Notification Inputs
Supports Four External Downstream Ports
Supports Vendor Requests to Read and Write I²C and EEPROM Read at 100 k
I²C Master Supports Clock Stretching
OTP ROM, Serial EEPROM or I²C/SMBus Slave Interface for Custom Configurations:
- VID and PID
- Port Customizations
- Manufacturer and Product Strings (not by OTP ROM)
- Serial Number (not by OTP ROM)
Application Feature Selection Using Pin Selection or EEPROM or I²C/SMBus Slave Interface
Provides 128-Bit Universally Unique Identifier (UUID)
Single Clock Input, 24-MHz Crystal or Oscillator
Downstream Ports Configurable to USB2.0 Only
64-Pin QFN Package (RGC)

2 Applications

Computer Systems, Docking Stations, Monitors, Set-Top Boxes

3 Description

The TUSB8041A is a four-port USB 3.1 Gen1 hub. It provides simultaneous SuperSpeed USB and high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or low-speed connections on the downstream ports. When the upstream port is connected to an electrical environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is disabled on the downstream ports.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TUSB8041A	VQFN (64)	9.00 mm × 9.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Diagram

4 Revision History

Table 1.

DATE	REVISION	NOTES
August 2017	*	Initial release.

5 Description (Continued)

When the upstream port is connected to an electrical environment that only supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the downstream ports.

The TUSB8041A supports per port or ganged power switching and over-current protection, and supports battery charging applications.

An individually port power controlled hub switches power on or off to each downstream port as requested by the USB host. Also when an individually port power controlled hub senses an over-current event, only power to the affected downstream port will be switched off.

A ganged hub switches on power to all its downstream ports when power is required to be on for any port. The power to the downstream ports is not switched off unless all ports are in a state that allows power to be removed. Also when a ganged hub senses an over-current event, power to all downstream ports will be switched off.

The TUSB8041A downstream ports provide support for battery charging applications by providing Battery Charging Downstream Port (CDP) handshaking support. It also supports a Dedicated Charging Port (DCP) mode when the upstream port is not connected. The DCP mode supports USB devices which support with the USB Battery Charging, and Chinese Telecommunications Industry Standard YD/T 1591-2009. In addition when upstream port is unconnected, the TUSB8041A supports the divider charging port modes (ACPx modes) and an automatic transition through all modes, starting with ACP2 and ending in DCP.

The TUSB8041A provides pin strap configuration for some features including battery charging support, and also provides customization though OTP ROM, I²C EEPROM, or via an I²C/SMBus slave interface for PID, VID, and custom port and phy configurations. Custom string support is also available when using an I²C EEPROM or the I²C/SMBus slave interface.

The device is available in a 64-pin RGC package and is offered in a commercial version for operation over the temperature range of 0°C to 70°C.

6 Pin Configuration and Functions

RGC Package

64 Pin (VQFN)

(Top View)

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
Clock and Reset Signals
GRSTz	50	I PU	Global power reset. This reset brings all of the TUSB8041A internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
XI	62	I	Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
XO	61	O	Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
USB Upstream Signals
USB_SSTXP_UP	55	O	USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP	56	O	USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP	58	I	USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP	59	I	USB SuperSpeed receiver differential pair (negative)
USB_DP_UP	53	I/O	USB High-speed differential transceiver (positive)
USB_DM_UP	54	I/O	USB High-speed differential transceiver (negative)
USB_R1	64	I	Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
USB_VBUS	48	I	USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground through a 10-kΩ ±1% resistor from the signal to ground.
USB Downstream Signals
USB_SSTXP_DN1	3	O	USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1	4	O	USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1	6	I	USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1	7	I	USB SuperSpeed receiver differential pair (negative)
USB_DP_DN1	1	I/O	USB High-speed differential transceiver (positive)
USB_DM_DN1	2	I/O	USB High-speed differential transceiver (negative)
PWRCTL1/BATEN1	36	I/O, PD	USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 1. This pin be left unconnected if power management is not implemented.
			In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register:
				0 = Battery charging not supported
				1 = Battery charging supported
OVERCUR1z	46	I, PU	USB Port 1 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 1.
				0 = An over current event has occurred
				1 = An over current event has not occurred
			When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN2	11	O	USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2	12	O	USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2	14	I	USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2	15	I	USB SuperSpeed receiver differential pair (negative)
USB_DP_DN2	9	I/O	USB High-speed differential transceiver (positive)
USB_DM_DN2	10	I/O	USB High-speed differential transceiver (negative)
PWRCTL2/BATEN2	35	I/O, PD	USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 2. This pin be left unconnected if power management is not implemented.
			In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 2 as indicated in the Battery Charging Support register:
				0 = Battery charging not supported
				1 = Battery charging supported
OVERCUR2z	47	I, PU	USB Port 2 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 2.
				0 = An over current event has occurred
				1 = An over current event has not occurred
			When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN3	19	O	USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3	20	O	USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3	22	I	USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3	23	I	USB SuperSpeed receiver differential pair (negative)
USB_DP_DN3	17	I/O	USB High-speed differential transceiver (positive)
USB_DM_DN3	18	I/O	USB High-speed differential transceiver (negative)
PWRCTL3/BATEN3	33	I/O, PD	USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 3. This pin be left unconnected if power management is not implemented.
			In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 3 as indicated in the Battery Charging Support register:
				0 = Battery charging not supported
				1 = Battery charging supported
OVERCUR3z	44	I, PU	USB Port 3 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 3.
				0 = An over current event has occurred
				1 = An over current event has not occurred
			When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN4	26	O	USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN4	27	O	USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN4	29	I	USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN4	30	I	USB SuperSpeed receiver differential pair (negative)
USB_DP_DN4	24	I/O	USB High-speed differential transceiver (positive)
USB_DM_DN4	25	I/O	USB High-speed differential transceiver (negative)
PWRCTL4/BATEN4	32	I/O, PD	USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 4. This pin be left unconnected if power management is not implemented.
			In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 4 as indicated in the Battery Charging Support register:
				0 = Battery charging not supported
				1 = Battery charging supported
OVERCUR4z	43	I, PU	USB Port 4 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 4.
				0 = An over current event has occurred
				1 = An over current event has not occurred
			When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
I²C/SMBUS I²C Signals
SCL/SMBCLK	38	I/O, PD	I²C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
				When SMBUSz = 1, this pin acts as the serial clock interface for an I²C EEPROM.
				When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
			Can be left unconnected if external interface not implemented.
SDA/SMBDAT	37	I/O, PD	I²C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
				When SMBUSz = 1, this pin acts as the serial data interface for an I²C EEPROM.
				When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
			Can be left unconnected if external interface not implemented.
SMBUSz/SS_SUSPEND	39	I/O, PU	I²C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled at the de-assertion of reset set I²C or SMBus mode as follows:
				1 = I²C Mode Selected
				0 = SMBus Mode Selected
			Can be left unconnected if external interface not implemented.
			After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
FULLPWRMGMTz / SMBA1/SS_UP	40	I/O, PD	Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status Upstream port. The value of the pin is sampled at the de-assertion of reset to set the power switch control: 0 = Power Switching and over current inputs supported. 1= Power Switch and over current inputs not supported. Full power management is the ability to control power to the downstream ports of the TUSB8041A using PWRCTL[4:1]/BATEN[4:1]. When SMBus mode is enabled, this pin sets the value of the SMBus slave address bit 1. Can be left unconnected if full power management and SMBus are not implemented. After reset, this signal indicates the SuperSpeed USB connection status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port. Note: Power switching must be supported for battery charging applications
PWRCTL_POL	41	I/O, PU	Power Control Polarity.
			The value of the pin is sampled at the de-assertion of reset to set the polarity of PWRCTL[4:1].
				0 = PWRCTL polarity is active low
				1 = PWRCTL polarity is active high
GANGED/SMBA2/ HS_UP	42	I/O, PD	Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port.
			The value of the pin is sampled at the de-assertion of reset to set the power switch and over current detection mode as follows:
				0 = Individual power control supported when power switching is enabled
				1 = Power control gangs supported when power switching is enabled
			When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 2.
			After reset, this signal indicates the High-speed USB connection status of the upstream port if enabled through the stsOutputEn bit in Additional Feature Configuration register. When enabled, a value of 1 indicates the upstream port is connected to a High-speed USB capable port.
			Note: Individual power control must be enabled for battery charging applications.
AUTOENz/ HS_SUSPEND	45	I/O, PU	Automatic Charge Mode Enable/HS Suspend Status.
			The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is enabled as follows:
				0 = Automatic Mode is enabled on ports that are enabled for battery charging when the hub is unconnected. Please note that CDP is not supported on Port 1 when operating in Automatic mode.
				1 = Automatic Mode is disabled
			This value is also used to set the autoEnz bit in the Battery Charging Support Register.
			After reset, this signal indicates the High-speed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended.
TEST	49	I, PD	This pin is reserved for factory test. It is suggested to have this pin pulled down to ground on PCB.
Power and Ground Signals
VDD	5, 8, 13, 21, 28, 31, 51, 57	PWR	1.1-V power rail
VDD33	16, 34, 52, 63	PWR	3.3-V power rail
VSS (Thermal Pad)		PWR	Ground. Thermal pad must be connected to ground.
NC	60	—	No connect, leave floating

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply Voltage Range	V_DD Steady-state supply voltage	–0.3	1.4	V
Supply Voltage Range	V_DD33 Steady-state supply voltage	–0.3	3.8	V
Voltage Range	USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals	-0.3	1.4	V
	XI terminals	-0.3	2.45	V
	All other terminals	-0.3	3.8	V
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
VDD⁽¹⁾	1.1V supply voltage		0.99	1.1	1.26	V
VDD33	3.3V supply voltage		3	3.3	3.6	V
USB_VBUS	Voltage at USB_VBUS PAD		0		1.155	V
T_A	Operating free-air temperature	TUSB8041A	0		70	°C
T_J	Operating junction temperature		–40		105	°C

(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TUSB8041A	UNIT
		RGC
		64 PINS
R_θ_JA	Junction-to-ambient thermal resistance	26	°C/W
R_θ_JCtop	Junction-to-case (top) thermal resistance	11.5	°C/W
R_θ_JB	Junction-to-board thermal resistance	5.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	5.2	°C/W
R_θ_JCbot	Junction-to-case (bottom) thermal resistance	1.0	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER		OPERATION	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	High-level input voltage⁽¹⁾	VDD33		2		VDD33	V
V_IL	Low-level input voltage⁽¹⁾	VDD33		0		0.8	V
V_I	Input voltage			0		VDD33	V
V_O	Output voltage⁽²⁾			0		VDD33	V
t_t	Input transition time (t_rise and t_fall)			0		25	ns
V_hys	Input hysteresis⁽³⁾					0.13 x VDD33	V
V_OH	High-level output voltage	VDD33	I_OH = -4 mA	2.4			V
V_OL	Low-level output voltage	VDD33	I_OL = 4 mA			0.4	V
I_OZ	High-impedance, output current⁽²⁾	VDD33	V_I = 0 to VDD33			±20	µA
I_OZP	High-impedance, output current with internal pullup or pulldown resistor⁽⁴⁾	VDD33	V_I = 0 to VDD33			±250	µA
I_I	Input current⁽⁵⁾	VDD33	V_I = 0 to VDD33			±15	µA
R_PD	Internal pull-down resister			13.5	19	27.5	KΩ
R_PU	Internal pull-up resistor			14.5	19	25	KΩ

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.

(3) Applies to GRSTz.

(4) Applies to pins with internal pullups/pulldowns.

(5) Applies to external input buffers.

7.6 Timing Requirements, Power-Up

PARAMETER	DESCRIPTION	MIN	MAX	UNIT
t_d1	VDD33 stable before VDD stable⁽³⁾	See ⁽²⁾		ms
t_d2	VDD and VDD33 stable before de-assertion of GRSTz	3		ms
t_{su_io}	Setup for MISC inputs⁽¹⁾ sampled at the de-assertion of GRSTz	0.1		µs
t_{hd_io}	Hold for MISC inputs⁽¹⁾ sampled at the de-assertion of GRSTz	0.1		µs
t_{VDD33_RAMP}	VDD33 supply ramp requirements	0.2	100	ms
t_{VDD_RAMP}	VDD supply ramp requirements	0.2	100	ms

(1) MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.

(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 µs before the VDD33.

(3) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.

Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at T_A = 25°C

PARAMETER	VDD33	VDD	UNIT
PARAMETER	3.3 V	1.1 V	UNIT
LOW POWER MODES
Power On (after Reset)	3	30	mA
Upstream Disconnect	3	24	mA
Suspend	3	30	mA
ACTIVE MODES (US state / DS State)
3.0 host / 1 SS Device and Hub in U1 / U2	45	240	mA
3.0 host / 1 SS Device and Hub in U0	45	356	mA
3.0 host / 2 SS Devices and Hub in U1 / U2	45	301	mA
3.0 host / 2 SS Devices and Hub in U0	45	457	mA
3.0 host / 3 SS Devices and Hub in U1 / U2	45	372	mA
3.0 host / 3 SS Devices and Hub in U0	45	563	mA
3.0 host / 4 SS Devices and Hub in U1 / U2	45	440	mA
3.0 host / 4 SS Devices and Hub in U0	45	672	mA
3.0 host / 1 SS Device in U0 and 1 HS Device	84	372	mA
3.0 host / 2 SS Devices in U0 and 2 HS Devices	95	512	mA
2.0 host / HS Device	45	55	mA
2.0 host / 4 HS Devices	76	74	mA