SLLSEW4A June   2017  – August 2017 TUSB8043

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics, 3.3-V I/O
    6. 7.6 Timing Requirements, Power-Up
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 I2C Programming Support Using Internal Hid to I2C Interface
        1. 8.3.3.1 SET REPORT (Output)
        2. 8.3.3.2 GET REPORT (Feature)
        3. 8.3.3.3 GET REPORT (Input)
      4. 8.3.4 One Time Programmable (OTP) Configuration
      5. 8.3.5 Clock Generation
      6. 8.3.6 Crystal Requirements
      7. 8.3.7 Input Clock Requirements
      8. 8.3.8 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
      22. 8.5.22 Manufacturer String Registers
      23. 8.5.23 Product String Registers
      24. 8.5.24 Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8043 Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8043 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGC|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TUSB8043 is a four-port USB 3.1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or low speed connections on the downstream port. The TUSB8043 can be used in any application that needs additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By using the TUSB8043, the notebook can increase the downstream port count to five.

9.2 Typical Application

9.2.1 Discrete USB Hub Product

A common application for the TUSB8043 is as a self powered standalone USB hub product. The product is powered by an external 5V DC Power adapter. In this application, using a USB cable TUSB8043 upstream port is plugged into a USB Host controller. The downstream ports of the TUSB8043 are exposed to users for connecting USB hard drives, cameras, flash drives, and so forth.

TUSB8043 discrete_USB_hub_8043_sllsew4.gif Figure 27. Discrete USB Hub Product

9.2.1.1 Design Requirements

Table 31. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDD Supply 1.1 V
VDD33 Supply 3.3 V
Upstream Port USB Support (SS, HS, FS) SS, HS, FS
Downstream Port 1 USB Support (SS, HS, FS, LS) SS, HS, FS, LS
Downstream Port 2 USB Support (SS, HS, FS, LS) SS, HS, FS, LS
Downstream Port 3 USB Support (SS, HS, FS, LS) SS, HS, FS, LS
Downstream Port 4 USB Support (SS, HS, FS, LS) SS, HS, FS, LS
Number of Removable external exposed Downstream Ports 4
Number of Non-Removable external exposed Downstream Ports 0
Full Power Management of Downstream Ports Yes. (FULLPWRMGMTZ = 0)
Individual Control of Downstream Port Power Switch Yes. (GANGED = 0)
Power Switch Enable Polarity Active High. (PWRCTL_POL = 1)
Battery Charge Support for Downstream Port 1 Yes
Battery Charge Support for Downstream Port 2 Yes
Battery Charge Support for Downstream Port 3 Yes
Battery Charge Support for Downstream Port 4 Yes
I2C EEPROM Support No
24MHz Clock Source Crystal

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Upstream Port Implementation

The upstream of the TUSB8043 is connected to a USB3 Type B connector. This particular example has GANGED pin and FULLPWRMGMTZ pin pulled low which results in individual power support each downstream port. The VBUS signal from the USB3 Type B connector is feed through a voltage divider. The purpose of the voltage divider is to make sure the level meets USB_VBUS input requirements

TUSB8043 upstream_port_imp_sllsew4.gif Figure 28. Upstream Port Implementation

9.2.1.2.2 Downstream Port 1 Implementation

The downstream port 1 of the TUSB8043 is connected to a USB3 Type A connector. With BATEN1 pin pulled up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on BATEN1 should be uninstalled.

TUSB8043 downstream_port1_imp_sllsew4.gif Figure 29. Downstream Port 1 Implementation

9.2.1.2.3 Downstream Port 2 Implementation

The downstream port 2 of the TUSB8043 is connected to a USB3 Type A connector. With BATEN2 pin pulled up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on BATEN2 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI performance when the grounds are shorted together.

TUSB8043 downstream_port2_imp_sllsew4.gif Figure 30. Downstream Port 2 Implementation

9.2.1.2.4 Downstream Port 3 Implementation

The downstream port3 of the TUSB8043 is connected to a USB3 Type A connector. With BATEN3 pin pulled up, Battery Charge support is enabled for Port 3. If Battery Charge support is not needed, then pull-up resistor on BATEN3 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI performance when the grounds are shorted together.

TUSB8043 downstream_port3_imp_sllsew4.gif Figure 31. Downstream Port 3 Implementation

9.2.1.2.5 Downstream Port 4 Implementation

The downstream port 4 of the TUSB8043 is connected to a USB3 Type A connector. With BATEN4 pin pulled up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then pull-up resistor on BATEN4 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI performance when the grounds are shorted together.

TUSB8043 downstream_port4_imp_sllsew4.gif Figure 32. Downstream Port 4 Implementation

9.2.1.2.6 VBUS Power Switch Implementation

This particular example uses the Texas Instruments TPS2561 Dual Channel Precision Adjustable Current-Limited power switch. For details on this power switch or other power switches available from Texas Instruments, refer to the Texas Instruments website.

TUSB8043 vbus_imp_sllset2.gif Figure 33. VBUS Power Switch Implementation

9.2.1.2.7 Clock, Reset, and Misc

The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2, PWRCTL3, and PWRCTL4) for a USB VBUS power switch. SMBUSz pin is also left unconnected which will select I2C mode. Both PWRCTL_POL and SMBUSz pins have internal pull-ups. The 1 µF capacitor on the GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the supply ramp of the two supplies the capacitor size may have to be adjusted.

TUSB8043 clock_reset_misc_8043_sllsew4.gif Figure 34. Clock, Reset, and Misc

9.2.1.2.8 TUSB8043 Power Implementation

TUSB8043 pwr_imp_sllsew4.gif Figure 35. TUSB8043 Power Implementation

9.2.1.3 Application Curves

TUSB8043 eye_us_sllsee4.gif
Figure 36. Upstream Port
TUSB8043 eye_ds2_sllsee4.gif
Figure 38. Downstream Port 2
TUSB8043 eye_ds4_sllsee4.gif
Figure 40. Downstream Port 4
TUSB8043 eye_hs_ds1_sllsee4.gif
Figure 42. High-Speed Downstream Port 1
TUSB8043 eye_hs_ds3_sllsee4.gif
Figure 44. High-Speed Downstream Port 3
TUSB8043 eye_ds1_sllsee4.gif
Figure 37. Downstream Port 1
TUSB8043 eye_ds3_sllsee4.gif
Figure 39. Downstream Port 3
TUSB8043 eye_hs_us_sllsee4.gif
Figure 41. High-Speed Upstream Port
TUSB8043 eye_hs_ds2_sllsee4.gif
Figure 43. High-Speed Downstream Port 2
TUSB8043 eye_hs_ds4_sllsee4.gif
Figure 45. High-Speed Downstream Port 4